Abstract: An optical transceiver includes an input assembly, an output port, a fiber patch panel, multiple first optical fibers and multiple second optical fibers. The input assembly is arranged on a circuit board and has a first input port and a second input port. The fiber patch panel is arranged between the input assembly and the output port, and has multiple first fiber patch slots and multiple second fiber patch slots. The first optical fibers are connected to the first input port and the output port. The first optical fiber passes through the first fiber patch slot and the second fiber patch slot. The second optical fibers are connected to the second input port and the output port. The second optical fiber passes through the first fiber patch slot and the second fiber patch slot. The second fiber patch slot accommodates the first optical fiber and the second optical fiber.

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump, a conductive cap over the conductive bump, and a passivation layer. The conductive pad is over the semiconductor substrate. The conductive bump is over the conductive pad, wherein the conductive bump has a stepped sidewall structure including a lower sidewall, an upper sidewall laterally offset from the lower sidewall, and an intermediary surface laterally extending from a bottom edge of the upper sidewall to a top edge of the lower sidewall. The conductive cap is over the conductive bump. The passivation layer is over the semiconductor substrate and laterally surrounds the conductive bump, wherein the passivation layer has a top surface higher than the intermediary surface of the stepped sidewall structure of the conductive bump and lower than a top surface of conductive cap.

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

Abstract: The disclosure provides an electronic device including a housing, a light-emitting element and a light diffusion structure. The housing includes a first light-transmitting hole and a second light-transmitting hole. The light-emitting element is disposed in the housing, and is aligned with the first light-transmitting hole. The light diffusion structure includes a first light diffusion layer and a second light diffusion layer. The first light diffusion layer is disposed between the housing and the light-emitting element, and comprises a first semi-transparent region and a first light-shielding region. The first semi-transparent region corresponds to the first light-transmitting hole, and the first light-shielding region surrounds the first semi-transparent region. The second light diffusion layer is disposed between the housing and the light-emitting element, and comprises a second semi-transparent region and a second light-shielding region.

Abstract: An electronic device is provided. The electronic device includes a housing, a first light-emitting module, a second light-emitting module, and a control unit. The housing includes a first light-emitting region and a second light-emitting region. The first light-emitting module includes a plurality of first light-emitting units arranged in the first light-emitting region in an array, and the first light-emitting unit includes a light-emitting ink layer. The second light-emitting module is disposed in the second light-emitting region. The control unit is electrically connected to the first light-emitting module and the second light-emitting module, and generates a first light-emitting signal and a second light-emitting signal in response to an instruction, to respectively control the first light-emitting module and the second light-emitting module to emit light.

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump, a conductive cap over the conductive bump, and a passivation layer. The conductive pad is over the semiconductor substrate. The conductive bump is over the conductive pad, wherein the conductive bump has a stepped sidewall structure including a lower sidewall, an upper sidewall laterally offset from the lower sidewall, and an intermediary surface laterally extending from a bottom edge of the upper sidewall to a top edge of the lower sidewall. The conductive cap is over the conductive bump. The passivation layer is over the semiconductor substrate and laterally surrounds the conductive bump, wherein the passivation layer has a top surface higher than the intermediary surface of the stepped sidewall structure of the conductive bump and lower than a top surface of conductive cap.

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

Abstract: A semiconductor device comprises a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump over the conductive pad, a conductive cap over the conductive bump, and a passivation layer over the semiconductor substrate and surrounding the conductive bump. A combination of the conductive bump and the conductive cap has a stepped sidewall profile. The passivation layer has an inner sidewall at least partially facing and spaced apart from an outer sidewall of the conductive bump.

Abstract: The present invention provides RUT analogs with various biological activities. In particular, the biological activities comprise anti-inflammatory activity, vasodilator effects, migration/invasion-suppressive activities, ability against damage due to remodeling between the epithelium and endothelium, collagen deposition and cardiac fibrosis suppress, Snail protein inhibitory effect, etc., which may improve cardiac, vasodilation, and lung functions. The RUT analogs disclosed herein also exhibit a lower cytotoxicity comparing to RUT.

Abstract: The electronic device provided includes a housing with two first through holes and two second through holes, a light guiding structure, and a light source. A first section is provided between the two first through holes, and a second section is provided between the two second through holes. The length of the first section is less than the length of the second section. The light guiding structure includes a light guiding layer, a diffusion layer, and a light adjusting layer. The light adjusting layer is disposed at the position of the first section. The light source is disposed at a position that corresponds to an intersection of the first section and the second section. Light emitted by the light source passes through the light transmitting portion and the intersection, and is separately emitted through the first through holes and the second through holes along the light transmitting portion.

Abstract: The electronic device provided includes a housing with two first through holes and two second through holes, a light guiding structure, and a light source. A first section is provided between the two first through holes, and a second section is provided between the two second through holes. The length of the first section is less than the length of the second section. The light guiding structure includes a light guiding layer, a diffusion layer, and a light adjusting layer. . The light adjusting layer is disposed at the position of the first section. The light source is disposed at a position that corresponds to an intersection of the first section and the second section. Light emitted by the light source passes through the light transmitting portion and the intersection, and is separately emitted through the first through holes and the second through holes along the light transmitting portion.

Abstract: The present disclosure discloses use of TM9SF1 gene as a target in vascular diseases, which relates to the field of biotechnology. In the present disclosure, by means of RNA interference strategy, it is found that after endogenous TM9SF1 gene is interfered with, the expression of two important genes IL1? and IL8 related to the inflammation of HUVEC and the expression of the gene ACE1 closely related to vasoconstriction are remarkably downregulated, suggesting that TM9SF1 gene has positive regulation effect on the expression of IL1?, IL8 and ACE1 genes. By inhibiting or silencing the expression of the TM9SF1 gene, it is possible to inhibit or silence the expression of IL1?, IL8, and ACE1 genes, and further achieve the object of treating or preventing vascular diseases associated with the expression level of IL1?, IL8 and ACE1 genes.