Patents by Inventor Chun Mao
Chun Mao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9123616Abstract: A method of fabricating a semiconductor image sensor device is disclosed. A plurality of radiation-sensing regions is formed in a substrate. The radiation-sensing regions are formed in a non-scribe-line region of the image sensor device. An opening is formed in a scribe-line region of the image sensor device by etching the substrate in the scribe-line region. A portion of the substrate remains in the scribe-line region after the etching. The opening is then filled with an organic material.Type: GrantFiled: July 3, 2014Date of Patent: September 1, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shou-Shu Lu, Hsun-Ying Huang, Hsin-Jung Huang, Chun-Mao Chiu, Chia-Chi Hsiao, Yung-Cheng Chang
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Patent number: 9117904Abstract: A semiconductor structure includes a substrate, a gate electrode disposed on the substrate, wherein the gate electrode has a first top surface. Agate dielectric layer is disposed between the substrate and the gate electrode. A silicon carbon nitride spacer surrounds the gate electrode, wherein the silicon carbon nitride spacer has a second top surface not higher than the first top surface. A silicon oxide spacer surrounds the silicon carbon nitride spacer.Type: GrantFiled: January 28, 2015Date of Patent: August 25, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shyan-Liang Chou, Tsung-Min Kuo, Po-Wen Su, Chun-Mao Chiou, Feng-Mou Chen
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Publication number: 20150137197Abstract: A semiconductor structure includes a substrate, a gate electrode disposed on the substrate, wherein the gate electrode has a first top surface. Agate dielectric layer is disposed between the substrate and the gate electrode. A silicon carbon nitride spacer surrounds the gate electrode, wherein the silicon carbon nitride spacer has a second top surface not higher than the first top surface. A silicon oxide spacer surrounds the silicon carbon nitride spacer.Type: ApplicationFiled: January 28, 2015Publication date: May 21, 2015Inventors: Shyan-Liang Chou, Tsung-Min Kuo, Po-Wen Su, Chun-Mao Chiou, Feng-Mou Chen
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Patent number: 9005922Abstract: The present invention discloses a sensor chip for screening a topoisomerase inhibitor and a screening method thereof. The sensor chip comprises topoisomerase I and a biochip. The topoisomerase I is immobilized on the biochip, and the topoisomerase I has DNA catalytic activity. This provides a rapid screening method for topoisomerase I inhibitors.Type: GrantFiled: September 21, 2010Date of Patent: April 14, 2015Assignee: Taipei Medical UniversityInventors: Chun-Mao Lin, Hsiang-Ping Tsai, Chwen-Ming Shih, Jau-Lang Hwang, Chi-Ming Lee
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Patent number: 8975673Abstract: A method of trimming spacers includes etching a silicon oxide spacer when forming an outmost spacer, so that a silicon carbon nitride spacer contacting the gate electrode exposes an area. The exposure area of the silicon carbon nitride spacer can then be partly removed by phosphate acid. At the end of the semiconductor process, at least part of the top surface of the silicon carbon nitride spacer will be lower than the top surface of a gate electrode.Type: GrantFiled: April 16, 2012Date of Patent: March 10, 2015Assignee: United Microelectronics Corp.Inventors: Shyan-Liang Chou, Tsung-Min Kuo, Po-Wen Su, Chun-Mao Chiou, Feng-Mou Chen
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Patent number: 8890218Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure disposed on the substrate; a first spacer disposed on a sidewall of the gate structure; a second spacer disposed around the first spacer, wherein the second spacer comprises a L-shaped cap layer and a cap layer on the L-shaped cap layer; a source/drain disposed in the substrate adjacent to two sides of the second spacer; and a CESL disposed on the substrate to cover the gate structure, wherein at least part of the second spacer and the CESL comprise same chemical composition and/or physical property.Type: GrantFiled: May 13, 2013Date of Patent: November 18, 2014Assignee: United Microelectronics Corp.Inventors: Chu-Chun Chang, Chun-Mao Chiou, Chiu-Te Lee
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Publication number: 20140322857Abstract: A method of fabricating a semiconductor image sensor device is disclosed. A plurality of radiation-sensing regions is formed in a substrate. The radiation-sensing regions are formed in a non-scribe-line region of the image sensor device. An opening is formed in a scribe-line region of the image sensor device by etching the substrate in the scribe-line region. A portion of the substrate remains in the scribe-line region after the etching. The opening is then filled with an organic material.Type: ApplicationFiled: July 3, 2014Publication date: October 30, 2014Inventors: Shou-Shu Lu, Hsun-Ying Huang, Huang-Hsin Jung, Chun-Mao Chiu, Chia-Chi Hsiao, Yung-Cheng Chang
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Patent number: 8841755Abstract: The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on a surface of the via opening. The barrier layer is disposed on a surface of the insulation layer. The buffer layer is disposed on a surface of the barrier layer. The conductive electrode is disposed on a surface of the buffer layer and a remainder of the via opening is completely filled with the conductive electrode. A portion of the buffer layer further covers a surface of the conductive electrode at a side of the second surface and said portion is level with the second surface.Type: GrantFiled: July 22, 2013Date of Patent: September 23, 2014Assignee: United Microelectronics Corp.Inventors: Kuo-Hsiung Huang, Chun-Mao Chiou, Hsin-Yu Chen, Yu-Han Tsai, Ching-Li Yang, Home-Been Cheng
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Patent number: 8772895Abstract: Provided is a semiconductor image sensor device that includes a non-scribe-line region and a scribe-line region. The image sensor device includes a first substrate portion disposed in the non-scribe-line region. The first substrate portion contains a doped radiation-sensing region. The image sensor device includes a second substrate portion disposed in the scribe-line region. The second substrate portion has the same material composition as the first substrate portion. Also provided is a method of fabricating an image sensor device. The method includes forming a plurality of radiation-sensing regions in a substrate. The radiation-sensing regions are formed in a non-scribe-line region of the image sensor device. The method includes forming an opening in a scribe-line region of the image sensor device by etching the substrate in the scribe-line region. A portion of the substrate remains in the scribe-line region after the etching. The method includes filling the opening with an organic material.Type: GrantFiled: November 28, 2011Date of Patent: July 8, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shou-Shu Lu, Hsun-Ying Huang, Hsin-Jung Huang, Chun-Mao Chiu, Chia-Chi Hsiao, Yung-Cheng Chang
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Patent number: 8692334Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.Type: GrantFiled: July 24, 2013Date of Patent: April 8, 2014Assignee: United Microelectronics Corp.Inventors: Chun-Mao Chiou, Ti-Bin Chen, Tsung-Min Kuo, Shyan-Liang Chou, Yao-Chang Wang, Chi-Sheng Tseng, Jie-Ning Yang, Po-Jui Liao
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Patent number: 8683743Abstract: The present invention discloses a grain germinating system comprising a temperature controlling device, an incubation device, a drying device and a monitoring device. The temperature controlling device comprises a heat pump module, an air conditioning module and a piping module. The heat pump module can output a high or low temperature heat exchanging liquid. The temperature of a culture medium of a grain is adjusted by the incubation device. The incubated grain is dried by the drying device. The air conditioning module is for a plant building. The piping module is connected with the heat pump module, and is provided for the high or low temperature heat exchanging liquid to flow. The incubation device and the drying device are heated by the high temperature heat exchanging liquid. The drying device is cooled by the low temperature heat exchanging liquid provided for the air condition of the plant building to use.Type: GrantFiled: March 22, 2010Date of Patent: April 1, 2014Assignee: Taipei Medical UniversityInventors: Chun-Mao Lin, Fu-Der Mai, Chien-Lung Hung, Chwen-Ming Shih
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Patent number: 8673755Abstract: A manufacturing method of a semiconductor device having metal gate includes providing a substrate having a first semiconductor device, a second semiconductor device, and a first insulating layer covering the first semiconductor device and the second semiconductor device formed thereon, performing an etching process to remove a portion of the first insulating layer to expose a portion of the first semiconductor device and the second semiconductor device, forming a second insulating layer covering the first semiconductor device and the second semiconductor device, performing a first planarization process to remove a portion of the second insulating layer, forming a first gate trench and a second gate trench respectively in the first semiconductor device and the second semiconductor device, and forming a first metal gate and a second metal gate respectively in the first gate trench and the second gate trench.Type: GrantFiled: October 27, 2011Date of Patent: March 18, 2014Assignee: United Microelectronics Corp.Inventors: Chu-Chun Chang, Kuang-Hung Huang, Chun-Mao Chiou, Yi-Chung Sheng
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Publication number: 20130307084Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.Type: ApplicationFiled: July 24, 2013Publication date: November 21, 2013Applicant: United Microelectronics Corp.Inventors: Chun-Mao Chiou, Ti-Bin Chen, Tsung-Min Kuo, Shyan-Liang Chou, Yao-Chang Wang, Chi-Sheng Tseng, Jie-Ning Yang, Po-Jui Liao
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Publication number: 20130299949Abstract: The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on a surface of the via opening. The barrier layer is disposed on a surface of the insulation layer. The buffer layer is disposed on a surface of the barrier layer. The conductive electrode is disposed on a surface of the buffer layer and a remainder of the via opening is completely filled with the conductive electrode. A portion of the buffer layer further covers a surface of the conductive electrode at a side of the second surface and said portion is level with the second surface.Type: ApplicationFiled: July 22, 2013Publication date: November 14, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsiung Huang, Chun-Mao Chiou, Hsin-Yu Chen, Yu-Han Tsai, Ching-Li Yang, Home-Been Cheng
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Publication number: 20130270613Abstract: A method of trimming spacers includes etching a silicon oxide spacer when forming an outmost spacer, so that a silicon carbon nitride spacer contacting the gate electrode exposes an area. The exposure area of the silicon carbon nitride spacer can then be partly removed by phosphate acid. At the end of the semiconductor process, at least part of the top surface of the silicon carbon nitride spacer will be lower than the top surface of a gate electrode.Type: ApplicationFiled: April 16, 2012Publication date: October 17, 2013Inventors: Shyan-Liang Chou, Tsung-Min Kuo, Po-Wen Su, Chun-Mao Chiou, Feng-Mou Chen
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Publication number: 20130256765Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure disposed on the substrate; a first spacer disposed on a sidewall of the gate structure; a second spacer disposed around the first spacer, wherein the second spacer comprises a L-shaped cap layer and a cap layer on the L-shaped cap layer; a source/drain disposed in the substrate adjacent to two sides of the second spacer; and a CESL disposed on the substrate to cover the gate structure, wherein at least part of the second spacer and the CESL comprise same chemical composition and/or physical property.Type: ApplicationFiled: May 13, 2013Publication date: October 3, 2013Inventors: Chu-Chun Chang, Chun-Mao Chiou, Chiu-Te Lee
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Publication number: 20130241002Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.Type: ApplicationFiled: March 14, 2012Publication date: September 19, 2013Inventors: Chun-Mao Chiou, Ti-Bin Chen, Tsung-Min Kuo, Shyan-Liang Chou, Yao-Chang Wang, Chi-Sheng Tseng, Jie-Ning Yang, Po-Jui Liao
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Patent number: 8524556Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.Type: GrantFiled: March 14, 2012Date of Patent: September 3, 2013Assignee: United Microelectronics Corp.Inventors: Chun-Mao Chiou, Ti-Bin Chen, Tsung-Min Kuo, Shyan-Liang Chou, Yao-Chang Wang, Chi-Sheng Tseng, Jie-Ning Yang, Po-Jui Liao
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Patent number: 8518823Abstract: The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on the surface of the via opening. The barrier layer is disposed on the surface of the insulation layer. The conductive electrode is disposed on the surface of the buffer layer and fills the via opening. The buffer layer further covers a surface of the conductive electrode at the side of the second surface. The present invention further discloses a method of forming the TSV.Type: GrantFiled: December 23, 2011Date of Patent: August 27, 2013Assignee: United Microelectronics Corp.Inventors: Kuo-Hsiung Huang, Chun-Mao Chiou, Hsin-Yu Chen, Yu-Han Tsai, Ching-Li Yang, Home-Been Cheng
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Publication number: 20130161796Abstract: The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on the surface of the via opening. The barrier layer is disposed on the surface of the insulation layer. The conductive electrode is disposed on the surface of the buffer layer and fills the via opening. The buffer layer further covers a surface of the conductive electrode at the side of the second surface. The present invention further discloses a method of forming the TSV.Type: ApplicationFiled: December 23, 2011Publication date: June 27, 2013Inventors: Kuo-Hsiung Huang, Chun-Mao Chiou, Hsin-Yu Chen, Yu-Han Tsai, Ching-Li Yang, Home-Been Cheng