Abstract: A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate, forming an isolation structure surrounding a lower portion of the fin structure, forming a protection layer over the isolation structure, etching the fin structure, the protection layer and the isolation structure to form a first recess in the fin structure and a second recess in the isolation structure, forming a source/drain feature to fill the first recess, and forming an interlayer dielectric layer over the source/drain feature and filling the second recess.

Abstract: A high electron mobility transistor includes a substrate, a mesa structure disposed on the substrate, a passivation layer disposed on the mesa structure, and at least a contact structure disposed in the passivation layer and the mesa structure. The mesa structure includes a channel layer, a barrier layer on the channel layer, two opposite first edges extending along a first direction, and two opposite second edges extending along a second direction. The contact structure includes a body portion and a plurality of protruding portions. The body portion penetrates through the passivation layer. The protruding portions penetrate through the barrier layer and a portion of the channel layer. In a top view, the body portion overlaps the two opposite first edges of the mesa structure without overlapping the two opposite second edges of the mesa structure.

Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.

Abstract: The invention provides method and system for improving efficiency of protecting multi-content process. The system may cooperate with a memory, and may comprise one or more hardware IPs (intellectual properties) for content processing, one of the one or more IPs may be associated with multiple access identities. The memory may comprise multiple different ranges, each range may register an access of one of the multiple access identities as a permissible access. The method may comprise: selecting one of the access identities for processing a first content, and using the selected access identity when said IP accesses the memory during processing of the first content; selecting a different one of the access identities for processing a second content, and using the selected different access identity when said IP accesses the memory during processing of the second content.

Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.

Abstract: A control system and a control method for speakers in a field are provided. The control method includes: outputting an audio signal by a first speaker corresponding to a first output power and a second speaker corresponding to a second output power; measuring a first volume and a first time delay corresponding to the audio signal by a first microphone; performing a calculation of an optimization algorithm according to the first output power, the second output power, the first volume, and the first time delay to obtain a first recommended output power corresponding to the first speaker and a second recommended output power corresponding to the second speaker; and configuring the first output power according to the first recommended output power, and configuring the second output power according to the second recommended output power.

Abstract: A method performed by a User Equipment (UE) for handling timing alignment is provided. The method receives, from a Base Station (BS), a first Radio Resource Control (RRC) message for configuring a Time Alignment Timer (TAT). The method receives, from the BS, a second RRC message for configuring at least one of a cell Discontinuous Transmission (DTX) operation or a cell Discontinuous Reception (DRX) operation. In a case that at least one of the cell DTX operation or the cell DRX operation is configured and the TAT expires, the method considers the UE to be uplink synchronized with the BS and forgoes performing a procedure for handling an out-of-sync condition related to the expiration of the TAT.

Abstract: A method performed by a User Equipment (UE) for Network Energy Saving (NES) is provided. The method receives, from a Base Station (BS), a Radio Resource Control (RRC) message including an NES configuration. The method then determines whether to apply a cell Discontinuous Transmission (DTX) operation, a cell Discontinuous Reception (DRX) operation, or both the cell DTX operation and the cell DRX operation based on the NES configuration.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first fin structure and a second fin structure. Each of the first fin structure and the second fin structure has multiple sacrificial layers and multiple semiconductor layers laid out in an alternating manner, and the first fin structure is substantially as wide as the second fin structure. The method also includes forming a gate stack wrapped around the first fin structure and the second fin structure. The method further includes simultaneously removing the sacrificial layers of the first fin structure and the second fin structure. Remaining portions of the semiconductor layers of the first fin structure form multiple first semiconductor nanostructures, and remaining portions of the semiconductor layers of the second fin structure form multiple second semiconductor nanostructures. Each of the first semiconductor nanostructures is thicker than each of the second semiconductor nanostructures.

Abstract: A method for forming a high electron mobility transistor is disclosed. A mesa structure having a channel layer and a barrier layer is formed on a substrate. The mesa structure has two first edges extending along a first direction and two second edges extending along a second direction. A passivation layer is formed on the substrate and the mesa structure. A first opening and a plurality of second openings connected to a bottom surface of the first opening are formed and through the passivation layer, the barrier layer and a portion of the channel layer. In a top view, the first opening exposes the two first edges of the mesa structure without exposing the two second edges of the mesa structure. A metal layer is formed in the first opening and the second openings thereby forming a contact structure.

Abstract: A semiconductor device includes an enhancement mode high electron mobility transistor (HEMT) with an active region and an isolation region. The HEMT includes a substrate, a group III-V body layer, a group III-V barrier layer and a recess. The group III-V body layer is disposed on the substrate. The group III-V barrier layer is disposed on the group III-V body layer in the active region and the isolation region. The recess is disposed in the group III-V barrier layer without penetrating the group III-V barrier layer in the active region.

Abstract: The present invention provides a method of forming an insulating structure of a high electron mobility transistor (HEMT), firstly, a gallium nitride layer is formed, next, an aluminum gallium nitride layer is formed on the gallium nitride layer, then, a first patterned photoresist layer is formed on the aluminum gallium nitride layer, and a groove is formed in the gallium nitride layer and the aluminum gallium nitride layer, next, an insulating layer is formed and filling up the groove. Afterwards, a second patterned photoresist layer is formed on the insulating layer, wherein the pattern of the first patterned photoresist layer is complementary to the pattern of the second patterned photoresist layer, and part of the insulating layer is removed, then, the second patterned photoresist layer is removed, and an etching step is performed on the remaining insulating layer to remove part of the insulating layer again.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer, forming a second barrier layer on the first barrier layer, forming a first hard mask on the second barrier layer, removing the first hard mask and the second barrier layer to form a recess; and forming a p-type semiconductor layer in the recess.

Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer, wherein the composition of the first III-V compound layer and the second III-V compound layer are different from each other. A source electrode and a drain electrode are disposed on the second III-V compound layer. A gate electrode is disposed on the second III-V compound layer between the source electrode and the drain electrode. An insulating layer is disposed between the drain electrode and the gate electrode and covering the second III-V compound layer. Numerous electrodes are disposed on the insulating layer and contact the insulating layer, wherein the electrodes are positioned between the gate electrode and the drain electrode and a distribution of the electrodes decreases along a direction toward the gate electrode.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a first hard mask on the first barrier layer; removing the first hard mask and the first barrier layer to form a recess; forming a second barrier layer in the recess; and forming a p-type semiconductor layer on the second barrier layer.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a second barrier layer on the first barrier layer; forming a first hard mask on the second barrier layer; removing the first hard mask and the second barrier layer to form a recess; and forming a p-type semiconductor layer in the recess.