Abstract: The invention provides a thermal uniformity compensating method and apparatus. The steps of the method includes: respectively measuring a plurality of first resistances of a plurality of hot spot patterns of a chip over an hot spot effect, wherein a plurality of pattern densities of the hot spot patterns are different; respectively measuring a plurality of second resistances of each of the hot spot patterns of the chip by a plurality of test keys over the hot spot effect, wherein a plurality of distances between the test keys and the corresponding hot spot pattern are different; establishing a look-up information according to the first and second resistances; analyzing a layout data of the chip for obtaining a pattern density information; and generating a calibrated layout data according to the pattern density information and the look-up information.

Abstract: The invention provides a thermal uniformity compensating method and apparatus. The steps of the method includes: respectively measuring a plurality of first resistances of a plurality of hot spot patterns of a chip over an hot spot effect, wherein a plurality of pattern densities of the hot spot patterns are different; respectively measuring a plurality of second resistances of each of the hot spot patterns of the chip by a plurality of test keys over the hot spot effect, wherein a plurality of distances between the test keys and the corresponding hot spot pattern are different; establishing a look-up information according to the first and second resistances; analyzing a layout data of the chip for obtaining a pattern density information; and generating a calibrated layout data according to the pattern density information and the look-up information.

Abstract: A layout structure of an electronic element including an electronic matrix, a first load and a second load is disclosed. The first load couples to a first end of the electronic matrix and includes a first testing pad and a second testing pad coupling to the first testing pad. The second load couples to a second end of the electronic matrix and includes a third testing pad and a fourth testing pad coupling to the third testing pad.

Abstract: An analytical synthesis method (ASM) for designing a higher-order voltage-mode operational trans-resistance amplifier and capacitor (OTRA-C) based filter is disclosed. A decomposition of a complicated nth-order transferring a function is converted into a set of equations corresponding to a set of sub-circuitries. Then, a circuit structure is constructed by combining said sub-circuitries.

Abstract: A semiconductor layout structure and a testing method thereof are disclosed. The semiconductor layout structure includes a device under test (DUT), a first testing pad, a second testing pad and a plurality of third testing pads. The DUT includes a plurality of metal-oxide-semiconductor (MOS) transistors. Each of the MOS transistors includes a first terminal, a second terminal and a third terminal. The first testing pad is coupled to the first terminals for being applied a first voltage. The second testing pad is coupled to the second terminals for being applied a second voltage. The third testing pads are respectively coupled to the third testing pads for being applied a third voltage. The third testing pads are electrical insulated from each other. The third voltage is larger than the first voltage and the second voltage.

Abstract: An analytical synthesis method (ASM) for designing a higher-order voltage-mode operational trans-resistance amplifier and capacitor (OTRA-C) based filter is disclosed. A decomposition of a complicated nth-order transferring a function is converted into a set of equations corresponding to a set of sub-circuitries. Then, a circuit structure is constructed by combining said sub-circuitries.

Abstract: A layout structure of an electronic element comprising an electronic matrix, a first load and a second load is disclosed. The first load couples to a first end of the electronic matrix and comprises a first testing pad and a second testing pad coupling to the first testing pad. The second load couples to a second end of the electronic matrix and comprises a third testing pad and a fourth testing pad coupling to the third testing pad.

Abstract: A complimentary single-ended-input OTA-C universal filter structures in terms of integrated circuits is provided. The integrated circuit comprises a plurality of amplifiers and a plurality of capacitors. In some capacitors, one electrode is electrically connected to the positive input of its corresponding amplifier, and the other electrode can be electrically connected to an electrical source. In addition, the negative input of one amplifier is electrically connected to the negative input of another amplifier. Besides, there are a head amplifier and a tail amplifier. The output of the head amplifier is electrically connected to the negative input of the head amplifier, and the positive input of the tail amplifier can be electrically connected to an electrical source.

Abstract: A method and a mechanism for nano scale patterns with high aspect ratios etched on both photoresist layers and a carrier substrate and uses two complementary photoresist layers as an etch mask and the laser direct-write lithography technology to quickly fabricate large-size & nano scale patterns features (1) inorganic photoresist as material of a first layer of photoresist for nano scale patterns defined by laser beam direct-write lithography and (2) polymeric organic photoresist as material of a second layer of photoresist to thicken an etch mask because of effect of oxygen plasma, which has a higher etching rate on a polymeric organic photoresist layer but a lower one on an inorganic photoresist layer. For various materials of carrier substrates applied to the present invention, there are several types of Inductively Coupled Plasma-Reactive Ion Etching technologies available for nano scale patterns continuously transferred to a carrier substrate.

Abstract: Nth-order voltage- and current-mode arbitrary phase shift oscillator structures are synthesized using n operational trans-conductance amplifiers (OTAs) or second-generation current controlled conveyors (CCCIIs) and n grounded capacitors. Linking up the I/O characteristics of the OTA and the CCCII and the reactance of grounded capacitor, the step of synthesis is first based on the algebraic analysis to oscillatory characteristic equations, resulting in a quadrature oscillator structure. Secondly, instead of the quadrature characteristic, to control each output signal with one another by a desired phase difference > or <90°, selectively superposing any of two fundamental OTA/CCCII-C sub-circuitries benefits the transformation of quadrature to arbitrary-phase-shift characteristic for the sinusoidal oscillator structure. Furthermore, several compensation schemes are presented for reducing the output parameter deviation due to the non-ideal effects.

Abstract: A structure of trench capacitor and method for manufacturing the trench capacitor is provided. The collar oxide layer of the trench capacitor is formed by a thermal oxidation process. Moreover, a protective layer such as silicon nitride covers the collar oxide layer. A failure analysis of the collar oxide layer can be operated by detecting the protective layer. If the protective layer is detected, the collar oxide layer is therefore at a suitable thickness. Furthermore, a mask layer rather than the collar oxide layer is used as a mask during the trench formation.

Abstract: A voltage-mode nth-order differential difference current conveyor (DDCC) and fully differential current conveyor (FDCCII)-resistor and capacitor filter structures are proposed using a new effective analytical synthesis method (ASM), a succession of innovative algebra operations until a set of simple equations are produced, which are then realized using n integrators and a constraint sub-circuitry, A new ASM can effectively carry out (i) use of all the grounded capacitors and grounded resistors, and (ii) employment of the minimum number of active and passive components and then enjoys the low sensitivities, lower parasitics, power consumption, noise, and smaller chip area leading to simultaneously achieving two important features: (i) higher output performance and (ii) lower cost, without tradeoff. Moreover, the component value variations of all the relative sensitivities have the same incremental percentage or decrement.

Abstract: A complimentary single-ended-input OTA-C universal filter structures in terms of integrated circuits is provided. The integrated circuit comprises a plurality of amplifiers and a plurality of capacitors. In some capacitors, one electrode is electrically connected to the positive input of its corresponding amplifier, and the other electrode can be electrically connected to an electrical source. In addition, the negative input of one amplifier is electrically connected to the negative input of another amplifier. Besides, there are a head amplifier and a tail amplifier. The output of the head amplifier is electrically connected to the negative input of the head amplifier, and the positive input of the tail amplifier can be electrically connected to an electrical source.

Abstract: Nth-order voltage- and current-mode arbitrary phase shift oscillator structures are synthesized using n operational trans-conductance amplifiers (OTAs) or second-generation current controlled conveyors (CCCIIs) and n grounded capacitors. Linking up the I/O characteristics of the OTA and the CCCII and the reactance of grounded capacitor, the step of synthesis is first based on the algebraic analysis to oscillatory characteristic equations, resulting in a quadrature oscillator structure. Secondly, instead of the quadrature characteristic, to control each output signal with one another by a desired phase difference > or <90°, selectively superposing any of two fundamental OTA/CCCII-C sub-circuitries benefits the transformation of quadrature to arbitrary-phase-shift characteristic for the sinusoidal oscillator structure. Furthermore, several compensation schemes are presented for reducing the output parameter deviation due to the non-ideal effects.

Abstract: The present invention provides a method for concentrating particles or molecules and an apparatus thereof. The apparatus comprises a substrate, a conducting granule having nano-pores or nano-channels capable of permitting ion permeation, an electrolyte solution comprising counter-ions having an opposite electric property to the conducting granule, and an external field. Wherein, particles or molecules to be concentrated have an identical electric property as the conducting granule at a predefined pH value, and are added into the electrolyte solution with the predefined pH value. While the external electric field is applied across the reservoir where the conducting granule is sitting, the counter-ions exit from the nano-pores or nano-channels and such that a transient ion super-concentration phenomenon occurs at an ejecting pole on the conducting granule so as to concentrate the particles or molecules. Hence the present invention has potential application in bead-based molecular assays.

Abstract: A structure of trench capacitor and method for manufacturing the trench capacitor is provided. The collar oxide layer of the trench capacitor is formed by a thermal oxidation process. Moreover, a protective layer such as silicon nitride covers the collar oxide layer. A failure analysis of the collar oxide layer can be operated by detecting the protective layer. If the protective layer is detected, the collar oxide layer is therefore at a suitable thickness. Furthermore, a mask layer rather than the collar oxide layer is used as a mask during the trench formation.

Abstract: An analytical Synthesis Method (ASM) is clearly and effectively demonstrated in the realization of current/voltage-mode Operational Trans-conductance Amplifier and Capacitor (OTA-C) circuits, where a complicated nth-order transfer function is manipulated and decomposed by a succession of innovative algebra operations until a set of simple equations are produced, which are then realized using n integrators and a constraint circuitry. The circuits realized includes voltage-mode nth-order OTA-C universal filter structures, tunable voltage/current-mode OTA-C universal biquad filters, voltage-mode odd/even-nth-order OTA-C elliptic filter structures, voltage/current-mode odd-nth-order OTA-C elliptic high-pass filter structures, and OTA-C quadrature oscillators. Some realized OTA-C circuits can be simplified to be OTA-only (OTA-parasiic C) circuits which fit for the operation at high frequencies.

Abstract: A voltage-mode nth-order differential difference current conveyor (DDCC) and fully differential current conveyor (FDCCII)-resistor and capacitor filter structures are proposed using a new effective analytical synthesis method (ASM), a succession of innovative algebra operations until a set of simple equations are produced, which are then realized using n integrators and a constraint sub-circuitry, A new ASM can effectively carry out (i) use of all the grounded capacitors and grounded resistors, and (ii) employment of the minimum number of active and passive components and then enjoys the low sensitivities, lower parasitics, power consumption, noise, and smaller chip area leading to simultaneously achieving two important features: (i) higher output performance and (ii) lower cost, without tradeoff. Moreover, the component value variations of all the relative sensitivities have the same incremental percentage or decrement.

Abstract: Nth-order OTA-C (Operational Transconductance Amplifiers and Capacitors) filter structures are realized by using the analytical synthesis method to achieve the following three important criteria simultaneously: filters use just n grounded capacitors, each of which is located at each of just n nodes in the realized circuit, because they use smaller area in the IC, and they can absorb equivalent shunt capacitive parasites; filters employ only single-ended-input OTAs to overcome the feed-through effects due to finite input parasitic capacitances associated with double-input OTAs to replace the same positions of the n given capacitors; and filters have the least number-of components (passive and active) for a given order to reduce power consumption, chip areas, and noise. Both the first and the second criteria lead to the minimum parasitic distortion and make the most precise output signals. And the third criterion produces the cheapest chip.

Abstract: Nth-order OTA-C (Operational Transconductance Amplifiers and Capacitors) filter structures are realized by using the analytical synthesis method to achieve the following three important criteria simultaneously: filters use just n grounded capacitors, each of which is located at each of just n nodes in the realized circuit, because they use smaller area in the IC, and they can absorb equivalent shunt capacitive parasites; filters employ only single-ended-input OTAs to overcome the feed-through effects due to finite input parasitic capacitances associated with double-input OTAs to replace the same positions of the n given capacitors; and filters have the least number-of components (passive and active) for a given order to reduce power consumption, chip areas, and noise. Both the first and the second criteria lead to the minimum parasitic distortion and make the most precise output signals. And the third criterion produces the cheapest chip.