Patents by Inventor Chun Ming (Jimmy) YEH

Chun Ming (Jimmy) YEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210083084
    Abstract: A semiconductor device includes an enhancement mode high electron mobility transistor (HEMT) with an active region and an isolation region. The HEMT includes a substrate, a group III-V body layer, a group III-V barrier layer and a recess. The group III-V body layer is disposed on the substrate. The group III-V barrier layer is disposed on the group III-V body layer in the active region and the isolation region. The recess is disposed in the group III-V barrier layer in the active region.
    Type: Application
    Filed: October 17, 2019
    Publication date: March 18, 2021
    Inventors: Chun-Ming Chang, Wen-Jung Liao
  • Publication number: 20210083704
    Abstract: A method of providing over-the-air assistance information for interference cancellation or suppression to the receiver is proposed. Under a first solution, a two-stage DCI (downlink control information) or SCI (sidelink control information) scheduling method is proposed. The set of first-stage DCI or SCI provides a part of scheduling information which is beneficial for interference cancellation or suppression and is broadcasted by a transmitter or scheduler to all receivers. The set of second-stage DCI or SCI includes the remaining scheduling information and is unicasted by a transmitter or scheduler to each receiver. Under a second solution, assistance information DCI for interference cancellation or suppression is broadcasted by a transmitter or scheduler to all receivers.
    Type: Application
    Filed: December 1, 2020
    Publication date: March 18, 2021
    Inventors: Pei-Kai Liao, Chun-Ming Kuo, Chien-Hwa Hwang, Jiann-Ching Guey
  • Publication number: 20210083085
    Abstract: A semiconductor device includes an enhancement mode high electron mobility transistor (HEMT) with an active region and an isolation region. The HEMT includes a substrate, a group III-V body layer, a group III-V barrier layer, a group III-V gate structure and a group III-V patterned structure. The group III-V body layer and the group III-V barrier layer are disposed on the substrate. The group III-V gate structure is disposed on the group III-V barrier layer within the active region. The group III-V patterned structure is disposed on the group III-V barrier layer within the isolation region. The composition of the group III-V patterned structure is the same as the composition of the group III-V gate structure.
    Type: Application
    Filed: October 22, 2019
    Publication date: March 18, 2021
    Inventors: Chun-Ming Chang, Wen-Jung Liao
  • Publication number: 20210074838
    Abstract: A method of forming an insulating structure of a high electron mobility transistor (HEMT) is provided, the method including: forming a gallium nitride layer, forming an aluminum gallium nitride layer on the gallium nitride layer, performing an ion doping step to dope a plurality of ions in the gallium nitride layer and the aluminum gallium nitride layer, forming an insulating doped region in the gallium nitride layer and the aluminum gallium nitride layer, forming two grooves on both sides of the insulating doped region, and filling an insulating layer in the two grooves and forming two sidewall insulating structures respectively positioned at two sides of the insulating doped region.
    Type: Application
    Filed: November 19, 2020
    Publication date: March 11, 2021
    Inventors: Chun-Ming Chang, Wen-Jung Liao
  • Publication number: 20210066484
    Abstract: An enhancement mode high electron mobility transistor (HEMT) includes a group III-V semiconductor body, a group III-V barrier layer and a gate structure. The group III-V barrier layer is disposed on the group III-V semiconductor body, and the gate structure is a stacked structure disposed on the group III-V barrier layer. The gate structure includes a gate dielectric and a group III-V gate layer disposed on the gate dielectric, and the thickness of the gate dielectric is between 15 nm to 25 nm.
    Type: Application
    Filed: October 8, 2019
    Publication date: March 4, 2021
    Inventors: Chih-Tung Yeh, Chun-Ming Chang, Bo-Rong Chen, Shin-Chuan Huang, Wen-Jung Liao, Chun-Liang Hou
  • Publication number: 20210063229
    Abstract: A liquid level monitoring system includes: a hardware unit with a tube to extend through a surface of a liquid; a processor unit generating control signals that respectively correspond to target frequencies; a sound generator unit generating, respectively based on the control signals, incident sound waves that transmit in the tube and that are reflected by the surface of the liquid to respectively form reflected sound waves; and a sensor unit for sensing the reflected sound waves to respectively generate feedback signals. The processor unit determines a maximum amplitude frequency based on the feedback signals, and calculates a level of the surface of the liquid based on the maximum amplitude frequency and a length of the tube.
    Type: Application
    Filed: May 28, 2020
    Publication date: March 4, 2021
    Inventors: CHUN-MING HUANG, CHEN-CHIA CHEN, CHIH-HSING LIN, CHIEN-MING WU
  • Patent number: 10924485
    Abstract: An electronic signing authorization method includes converting a signing request submitted by an end user into a predetermined format, verifying an identity of an authorizing user of an authorization layer according to a predetermined verification process, accepting input data of the authorizing user of the authorization layer when the identity of the authorizing user of the authorization layer is verified, and outputting an authorization command according to the input data when the input data includes authorization data. The predetermined format includes at least one of a text format, an audio format, or a video format. The authorization command corresponds to rejecting the signing request, not authorizing the signing request, or authorizing the signing request.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: February 16, 2021
    Assignees: Interface Technology (ChengDu) Co., Ltd., INTERFACE OPTOELECTRONICS (SHENZHEN) CO., LTD., GENERAL INTERFACE SOLUTION LIMITED
    Inventors: Hsien-Ying Chou, Chun-Ming Chen, Tzu-Hsiang Lin
  • Patent number: 10921937
    Abstract: A touch panel includes a substrate, a plurality of first electrodes, a plurality of first bridge portions, and a plurality of second electrodes on the substrate. A plurality of connecting pads is on a side of the second electrodes away from the substrate. The connecting pads are made of a non-transparent conductive material. An insulating layer is on the substrate and covers the first electrodes, the first bridge portions, and the second electrodes. The insulating layer defines a plurality of through holes. Each connecting pad is exposed from the insulating layer by one through hole. A plurality of second bridge portions is on a side of the insulating layer away from the substrate. Each of the second bridge portions extends into adjacent two through holes to electrically couple adjacent two second electrodes.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: February 16, 2021
    Assignees: Interface Technology (ChengDu) Co., Ltd., INTERFACE OPTOELECTRONICS (SHENZHEN) CO., LTD., GENERAL INTERFACE SOLUTION LIMITED
    Inventor: Chun-Ming Chen
  • Publication number: 20210036138
    Abstract: A high electron mobility transistor (HEMT) includes a substrate; a buffer layer over the substrate, a GaN layer over the buffer layer, a first AlGaN layer over the GaN layer, a first AlN layer over the AlGaN layer, and a p-GaN layer over the first AlN layer.
    Type: Application
    Filed: September 3, 2019
    Publication date: February 4, 2021
    Inventors: Chun-Ming Chang, Chun-Liang Hou, Wen-Jung Liao
  • Publication number: 20210023742
    Abstract: A method is provided for manufacturing recyclable environment-friendly organic paper, in which a biomass plastic material, which is one of a biodegradable plastic (such as PLA), a biobased plastic (such as NPP), and a mixture of the two is used as a primary raw material, and the biomass plastic material and an inorganic mineral material (such as inorganic glass powder, mineral powder, and sand) and a bioplastic assisting agent (such as starch, apple pulp, egg shell, and the likes) are directly deposited into a compression and extension paper making machine to make environment-friendly organic paper. The environment-friendly organic paper so made does not contain fossil organic material (such as polypropylene), and thus no high temperature, smoke, and toxicant gases will be generated during burning and combustion and residuals of burning and combustion are primarily the natural inorganic minerals fraction can return to the earth and the nature.
    Type: Application
    Filed: July 25, 2019
    Publication date: January 28, 2021
    Inventor: Chun Ming Huang
  • Publication number: 20210023743
    Abstract: A method is provided for manufacturing recyclable inorganic paper, which has a composition comprising 60-85 wt % mixture of natural inorganic mineral powders, inorganic glass powders, and sand powders, 5-40 wt % bonding agent of polypropylene (PP), and 1-5 wt % assisting agents, through the following steps: feeding and mixing of the constituents of the composition; stirring and mixing the composition; pressing to cause bi-directional extension of the composition so as to form a sheet; subjecting the sheet to operation of a high density squeezing machine for further mixing and pressing the sheet; reversely turning and shaping the sheet for further extension of the sheet; and continuous compression and extension of the sheet to induce further bi-directional extension of the sheet in both lateral and longitudinal direction and to control thickness of the sheet.
    Type: Application
    Filed: July 25, 2019
    Publication date: January 28, 2021
    Inventor: Chun Ming Huang
  • Publication number: 20210020768
    Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A source electrode and a drain electrode are disposed on the second III-V compound layer. The gate electrode is disposed on the second III-V compound layer between the source electrode and the drain electrode. An insulating layer is disposed between the drain electrode and the gate electrode and covers the second III-V compound layer. At least one electrode is disposed on the insulating layer and contacts the insulating layer, wherein a voltage is applied to the electrode.
    Type: Application
    Filed: August 7, 2019
    Publication date: January 21, 2021
    Inventors: Chun-Ming Chang, Chih-Tung Yeh
  • Publication number: 20210011272
    Abstract: A medical/surgical microscope with two cameras configured to capture two dimensional images of specimens being observed. The medical/surgical microscope is secured to a control apparatus configured to adjust toe-in of the two cameras to insure the convergence of the images. The medical/surgical microscope includes a computer system with a non-transitory memory apparatus for storing computer program code configured for digitally rendering real-world medical/surgical images. The medical/surgical microscope has an illumination system with controls for focusing and regulating the lighting of a specimen. The medical/surgical microscope is configured for real-time video display with the function of recording and broadcasting simultaneously during surgery.
    Type: Application
    Filed: July 9, 2019
    Publication date: January 14, 2021
    Inventors: Chun-Ming Ko, Jianhung Tsai
  • Publication number: 20210013332
    Abstract: An insulating structure of a high electron mobility transistor (HEMT) is provided, which comprises a gallium nitride layer, an aluminum gallium nitride layer disposed on the gallium nitride layer, a groove disposed in the gallium nitride layer and the aluminum gallium nitride layer, an insulating layer disposed in the groove, wherein a top surface of the insulating layer is aligned with a top surface of the aluminum gallium nitride layer, and a passivation layer, disposed on the aluminum gallium nitride layer and the insulating layer.
    Type: Application
    Filed: July 23, 2019
    Publication date: January 14, 2021
    Inventors: Chun-Ming Chang, Wen-Jung Liao
  • Publication number: 20210013335
    Abstract: An insulating structure of a high electron mobility transistor (HEMT) is provided, which comprises a gallium nitride layer, an aluminum gallium nitride layer disposed on the gallium nitride layer, an insulating doped region disposed in the gallium nitride layer and the aluminum gallium nitride layer, and two sidewall insulating structures disposed at two sides of the insulating doped region respectively.
    Type: Application
    Filed: July 29, 2019
    Publication date: January 14, 2021
    Inventors: Chun-Ming Chang, Wen-Jung Liao
  • Publication number: 20210007320
    Abstract: An intelligent defecation device for living creature includes a device body, a supporting portion, an image module, and a first analysis module. The supporting portion is formed within the inner side of the device body for accommodating a moisture absorption member so as to allow the living creature to leave over its excrement therein. The image module is also arranged at the device body for dynamically capturing the images of the excrement in the supporting portion and outputting the image. The first analysis module is arranged in the device body and connected with the image module to analyze and calculate the defecation mode with the image based on preset or accumulated data, so as to generate a signal when an abnormal defecation mode is diagnosed.
    Type: Application
    Filed: June 11, 2020
    Publication date: January 14, 2021
    Inventors: James Cheng-Han Wu, Pei-Hsuan Shih, Chun-Ming Su, You-Gang Kuo, Ning-Yuan Lyu, Chi-Yeh Hsu, Liang-Hao Huang
  • Publication number: 20210013334
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.
    Type: Application
    Filed: August 7, 2019
    Publication date: January 14, 2021
    Inventors: Shin-Chuan Huang, Chih-Tung Yeh, Chun-Ming Chang, Bo-Rong Chen, Wen-Jung Liao, Chun-Liang Hou
  • Patent number: 10892358
    Abstract: An insulating structure of a high electron mobility transistor (HEMT) is provided, which comprises a gallium nitride layer, an aluminum gallium nitride layer disposed on the gallium nitride layer, an insulating doped region disposed in the gallium nitride layer and the aluminum gallium nitride layer, and two sidewall insulating structures disposed at two sides of the insulating doped region respectively.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: January 12, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ming Chang, Wen-Jung Liao
  • Patent number: 10886958
    Abstract: A method of providing over-the-air assistance information for interference cancellation or suppression to the receiver is proposed. Under a first solution, a two-stage DCI (downlink control information) or SCI (sidelink control information) scheduling method is proposed. The set of first-stage DCI or SCI provides a part of scheduling information which is beneficial for interference cancellation or suppression and is broadcasted by a transmitter or scheduler to all receivers. The set of second-stage DCI or SCI includes the remaining scheduling information and is unicasted by a transmitter or scheduler to each receiver. Under a second solution, assistance information DCI for interference cancellation or suppression is broadcasted by a transmitter or scheduler to all receivers.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: January 5, 2021
    Assignee: MediaTek INC.
    Inventors: Pei-Kai Liao, Chun-Ming Kuo, Chien-Hwa Hwang, Jiann-Ching Guey
  • Patent number: 10867116
    Abstract: Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yang-Hung Chang, Che-Yuan Sun, Chih-Ming Ke, Chun-Ming Hu