Patents by Inventor Chun Ming (Jimmy) YEH

Chun Ming (Jimmy) YEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11315586
    Abstract: A speech enhancement apparatus is disclosed and comprises an adaptive noise cancellation circuit, a blending circuit, a noise suppressor and a control module. The ANC circuit filters a reference signal to generate a noise estimate and subtracts a noise estimate from a primary signal to generate a signal estimate based on a control signal. The blending circuit blends the primary signal and the signal estimate to produce a blended signal. The noise suppressor suppresses noise over the blended signal using a first trained model to generate an enhanced signal and a main spectral representation from a main microphone and M auxiliary spectral representations from M auxiliary microphones using (M+1) second trained models to generate a main score and M auxiliary scores. The ANC circuit, the noise suppressor and the trained models are well combined to maximize the performance of the speech enhancement apparatus.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: April 26, 2022
    Assignee: British Cayman Islands Intelligo Technology Inc.
    Inventors: Bing-Han Huang, Chun-Ming Huang, Te-Lung Kung, Hsin-Te Hwang, Yao-Chun Liu, Chen-Chu Hsu, Tsung-Liang Chen
  • Patent number: 11309372
    Abstract: An organic light-emitting diode (OLED) display may have an array of organic light-emitting diode pixels that each have OLED layers interposed between a cathode and an anode. Voltage may be applied to the anode of each pixel to control the magnitude of emitted light. The conductivity of the OLED layers may allow leakage current to pass between neighboring anodes in the display. To reduce leakage current and the accompanying cross-talk in a display, the pixel definition layer may disrupt continuity of the OLED layers. The pixel definition layer may have a steep sidewall, a sidewall with an undercut, or a sidewall surface with a plurality of curves to disrupt continuity of the OLED layers. A control gate that is coupled to a bias voltage and covered by gate dielectric may be used to form an organic thin-film transistor that shuts the leakage current channel between adjacent anodes on the display.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: April 19, 2022
    Assignee: Apple Inc.
    Inventors: Jaein Choi, Andrew Lin, Cheuk Chi Lo, Chun-Yao Huang, Gloria Wong, Hairong Tang, Hitoshi Yamamoto, James E. Pedder, KiBeom Kim, Kwang Ohk Cheon, Lei Yuan, Michael Slootsky, Rui Liu, Steven E. Molesa, Sunggu Kang, Wendi Chang, Chun-Ming Tang, Cheng Chen, Ivan Knez, Enkhamgalan Dorjgotov, Giovanni Carbone, Graham B. Myhre, Jungmin Lee
  • Publication number: 20220109058
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a second barrier layer on the first barrier layer; forming a first hard mask on the second barrier layer; removing the first hard mask and the second barrier layer to form a recess; and forming a p-type semiconductor layer in the recess.
    Type: Application
    Filed: December 14, 2021
    Publication date: April 7, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ming Chang, Che-Hung Huang, Wen-Jung Liao, Chun-Liang Hou, Chih-Tung Yeh
  • Publication number: 20220097203
    Abstract: A calibration system, a calibration method, and a calibration device configured to determine base information of a polish head to polish a workpiece through the polish head are provided. The base information comprises a first position. The calibration system includes the polish head, a controller, and a sensor group. The controller is coupled to the polish head and controls the polish head to move along a first direction. The sensor group detects a force that at least one of the polish head and the workpiece senses to generate a first pressure value. The controller determines whether the first pressure value is greater than a predetermined value. According to that the first pressure value is greater than the predetermined value, the first position is determined.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 31, 2022
    Inventors: YUAN-KUN YANG, HAN-CHIEH CHANG, CHUN-MING ZHONG, HAI-JUN LI
  • Publication number: 20220101790
    Abstract: Systems and methods may reduce or eliminate image artifacts due to a defective pixel of an electronic display. An electronic display may include pixels that respectively include a self-emissive element, pixel drive circuitry that supplies a pixel drive current to drive the self-emissive element, and signal routing circuitry that reduces or eliminates a visual artifact due to a defective pixel among the pixels. The signal routing circuitry may do this by turning off the self-emissive element, supplying image data from the pixel drive circuitry to a first adjacent pixel, or receiving image data from other pixel drive circuitry from the first adjacent pixel or a second adjacent pixel.
    Type: Application
    Filed: September 10, 2021
    Publication date: March 31, 2022
    Inventors: John T. Wetherell, Cheuk Chi Lo, Chun-Yao Huang, Lingtao Wang, Derek Keith Shaeffer, Henry C. Jen, Hasan Akyol, Xuebei Yang, Chung-Lun Edwin Hsu, Patrick Bryce Bennett, Chun-Ming Tang, Yingkan Lin, Sheng Zhang, Chaohao Wang, Runjie Xu, Shingo Hatanaka
  • Publication number: 20220102152
    Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.
    Type: Application
    Filed: September 30, 2020
    Publication date: March 31, 2022
    Inventors: Wen-Ju Chen, Chung-Ting Ko, Wan-Chen Hsieh, Chun-Ming Lung, Tai-Chun Huang, Chi On Chui
  • Publication number: 20220097204
    Abstract: A polishing system for polishing a workpiece includes a sensor group detecting pressure information of the workpiece and generating a pressure sequence; a processor coupled to the sensor group and configured to: receive the pressure sequence; generate indication information including a predetermined track of a polishing head to polish the workpiece; based on the pressure sequence and the indication information, generate a deviation sequence of the pressure sequence; and based on the deviation sequence, generate an adjustment instruction, to adjust a position of the polishing head. A polishing method, an assistant polishing device, an assistant polishing system, and an assistant polishing method are also disclosed.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 31, 2022
    Inventors: YUAN-KUN YANG, XIAO-MING XU, HAN-CHIEH CHANG, BO LONG, HAI-JUN LI, CHUN-MING ZHONG
  • Publication number: 20220100103
    Abstract: Semiconductor processing apparatuses and methods are provided in which a semiconductor wafer is flipped and then rotated between patterning of front and back sides of the semiconductor wafer by first and second reticles, respectively. In some embodiments, a method includes patterning, by a first reticle, a first layer on a first side of a semiconductor wafer while the first side of the semiconductor wafer is facing a first direction. The semiconductor wafer is then flipped. A second side of the semiconductor wafer that is opposite the first side faces the first direction after the flipping the semiconductor wafer. The semiconductor wafer is then rotated about a rotational axis extending along the first direction, and a second layer on the second side of the semiconductor wafer is patterned by a second reticle.
    Type: Application
    Filed: March 10, 2021
    Publication date: March 31, 2022
    Inventors: Hung-Chung CHIEN, Hao-Ken HUNG, Chih-Chieh YANG, Ming-Feng SHIEH, Chun-Ming HU
  • Publication number: 20220102142
    Abstract: A method includes depositing a hard mask over a target layer. Depositing the hard mask includes depositing a first hard mask layer having a first density and depositing a second hard mask layer over the first hard mask layer, the second hard mask layer having a second density greater than the first density. The method further includes forming a plurality of mandrels over the hard mask; depositing a spacer layer over and along sidewalls of the plurality of mandrels; patterning the spacer layer to provide a plurality of spacers on the sidewalls of the plurality of mandrels; after patterning the spacer layer, removing the plurality of mandrels; transferring a patterning the plurality of spacers to the hard mask; and patterning the target layer using the hard mask as a mask.
    Type: Application
    Filed: January 19, 2021
    Publication date: March 31, 2022
    Inventors: Chun-Ming Lung, ChunYao Wang
  • Patent number: 11287746
    Abstract: Semiconductor processing apparatuses and methods are provided in which a semiconductor wafer is flipped and then rotated between patterning of front and back sides of the semiconductor wafer by first and second reticles, respectively. In some embodiments, a method includes patterning, by a first reticle, a first layer on a first side of a semiconductor wafer while the first side of the semiconductor wafer is facing a first direction. The semiconductor wafer is then flipped. A second side of the semiconductor wafer that is opposite the first side faces the first direction after the flipping the semiconductor wafer. The semiconductor wafer is then rotated about a rotational axis extending along the first direction, and a second layer on the second side of the semiconductor wafer is patterned by a second reticle.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Chung Chien, Hao-Ken Hung, Chih-Chieh Yang, Ming-Feng Shieh, Chun-Ming Hu
  • Patent number: 11268845
    Abstract: A liquid level monitoring system includes: a hardware unit with a tube to extend through a surface of a liquid; a processor unit generating control signals that respectively correspond to target frequencies; a sound generator unit generating, respectively based on the control signals, incident sound waves that transmit in the tube and that are reflected by the surface of the liquid to respectively form reflected sound waves; and a sensor unit for sensing the reflected sound waves to respectively generate feedback signals. The processor unit determines a maximum amplitude frequency based on the feedback signals, and calculates a level of the surface of the liquid based on the maximum amplitude frequency and a length of the tube.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: March 8, 2022
    Assignee: National Applied Research Laboratories
    Inventors: Chun-Ming Huang, Chen-Chia Chen, Chih-Hsing Lin, Chien-Ming Wu
  • Patent number: 11267129
    Abstract: An automatic positioning method and an automatic control device are provided. The automatic control device includes a processing unit, a memory unit, and a camera unit to automatically control a robotic arm. When the processing unit executes a positioning procedure, the camera unit obtains a first image of the robotic arm. The processing unit analyzes the first image to establish a three-dimensional working environment model and obtains first spatial positioning data. The processing unit controls the robotic arm to move a plurality of times to sequentially obtain a plurality of second images of the robotic arm by the camera unit and analyzes the second images and encoder information of the robotic arm to obtain second spatial positioning data. The processing unit determines whether an error parameter between the first spatial positioning data and the second spatial positioning data is less than a specification value to end the positioning procedure.
    Type: Grant
    Filed: November 28, 2019
    Date of Patent: March 8, 2022
    Assignee: Metal Industries Research & Development Centre
    Inventors: Shi-Wei Lin, Chun-Ming Yang, Fu-I Chou, Wan-Shan Yin
  • Patent number: 11264492
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: March 1, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shin-Chuan Huang, Chih-Tung Yeh, Chun-Ming Chang, Bo-Rong Chen, Wen-Jung Liao, Chun-Liang Hou
  • Publication number: 20220058109
    Abstract: A method for debugging a program, based on simulating an object program and comparing simulated waveforms with standard waveforms are applied in an electronic device. A simulated environment corresponding to the object program is established and multiple instructions from code of the object program are mapped against the standard waveforms. Trigger points are set in the object program, the object program is run from the trigger point and simulation waveforms are stored. The simulation waveforms are compared with the standard waveforms, and the location of a bug of the object program is found according a comparison. The bug may be resolved or cured. The electronic device utilizing the method is also disclosed.
    Type: Application
    Filed: August 17, 2021
    Publication date: February 24, 2022
    Inventors: CHUN-MING LU, CHIEN-FA CHEN
  • Publication number: 20220059607
    Abstract: A display apparatus including at least one driving circuit board, a plurality of light-emitting units, and a light-shielding layer is provided. The light-emitting units are disposed on a surface of the at least one driving circuit board and respectively have a plurality of pixel areas. The light-shielding layer is disposed on the at least one driving circuit board and disposed between the light-emitting units. The light-emitting units each have a circuit layer and a plurality of micro light-emitting devices. The circuit layer is electrically bonded to one of the at least one driving circuit board. The plurality of micro light-emitting devices are disposed on a side of the circuit layer away from the at least one driving circuit board and electrically bonded to the circuit layer. The micro light-emitting devices are respectively located in the pixel areas. A method of fabricating the display apparatus is also provided.
    Type: Application
    Filed: February 25, 2021
    Publication date: February 24, 2022
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: LOGANATHAN MURUGAN, Sheng-Yuan Sun, Chun-Ming Tseng, Yi-Chun Shih
  • Publication number: 20220059608
    Abstract: A spliced micro light-emitting-diode display panel includes multiple circuit boards spliced with each other and multiple micro light-emitting-diode modules. Each circuit board includes at least one driver IC. The micro light-emitting-diode modules are disposed separately on each circuit board and are electrically connected to the driver IC. Each micro light-emitting-diode module includes multiple light-emitting-diode units arranged in an array. On each circuit board, the driver IC drives the light-emitting-diode units of the micro light-emitting-diode modules to emit light. There is a first gap between any adjacent two of the light-emitting-diode units on any adjacent two of the circuit boards, and there is a second gap between any adjacent two of the light-emitting-diode units on each micro light-emitting-diode module, and the first gap is smaller than the second gap.
    Type: Application
    Filed: April 1, 2021
    Publication date: February 24, 2022
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Chun-Ming Tseng, Wei-Ping Lin, Gwo-Jiun Sheu
  • Publication number: 20220059511
    Abstract: The micro light-emitting diode (LED) display matrix module of the disclosure includes a multilayer circuit layer, multiple micro LEDs, and an insulating flat layer. The multilayer circuit layer includes a top circuit layer and a bottom circuit layer. The bottom circuit layer includes multiple pads. The micro LEDs are disposed on the top circuit layer of the multilayer circuit layer and define multiple light-emitting units. Each of the light-emitting units includes three of the micro LEDs that are separated from each other. The light-emitting units are arranged in a matrix of m columns and n rows to define multiple pixel regions, and quantity of the pads is equal to 3m+n. An orthographic projection of each of the micro LEDs on the bottom circuit layer completely overlaps the corresponding pad. The insulating flat layer covers the top circuit layer of the multilayer circuit layer and the micro LEDs.
    Type: Application
    Filed: April 12, 2021
    Publication date: February 24, 2022
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Wei-Ping Lin, Chun-Ming Tseng, Po-Jen Su
  • Publication number: 20220058994
    Abstract: A display apparatus includes a first circuit board and a plurality of first light emitting display units. The first circuit board has a first surface and a first board edge connected to the first surface. The first light emitting display units are disposed on the first surface. Each of the first light emitting display units has a plurality of first pixel areas and includes a first driving circuit layer electrically bonded to the first circuit board and a plurality of first light emitting devices. The first light emitting devices are disposed on one side of the first driving circuit layer away from the first circuit board and are electrically bonded to the first driving circuit layer. At least one of the first light emitting display units has a first side edge parallel to the first board edge. The first board edge is drawn back from the first side edge.
    Type: Application
    Filed: February 25, 2021
    Publication date: February 24, 2022
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Chun-Ming Tseng, Wei-Ping Lin, Po-Jen Su, Gwo-Jiun Sheu
  • Patent number: 11257142
    Abstract: A makeup evaluation computing device obtains a request from a user to initiate a makeup evaluation session. The makeup evaluation computing device initiates the makeup evaluation session without obtaining login credentials from the user and obtains a digital image of a facial region of the user. The makeup evaluation computing device generates a user interface displaying at least one cosmetic product and obtains from the user a selection of cosmetic products among the one or more displayed cosmetic products. The makeup evaluation computing device performs virtual application of the selected cosmetic products on the facial region of the user and stores the selection of cosmetic products. The makeup evaluation computing device generates a makeup session packet comprising the digital image of the facial region of the user and stored selection of cosmetic products. The makeup evaluation computing device transmits the makeup session packet to a cloud server and terminates the makeup evaluation session.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: February 22, 2022
    Assignee: PERFECT MOBILE CORP.
    Inventors: Chun Ming (Jimmy) Yeh, Chia Yu (Nick) TUNG (Dong)
  • Publication number: 20220052166
    Abstract: A high electron mobility transistor (HEMT) and method for forming the same are disclosed. The high electron mobility transistor includes a substrate, a mesa structure disposed on the substrate, a passivation layer disposed on the mesa structure, and at least a contact structure disposed in the passivation and the mesa structure. The mesa structure includes a channel layer and a barrier layer disposed on the channel layer. The contact structure includes a body portion and a plurality of protruding portions. The body portion is through the passivation layer. The protruding portions connect to a bottom surface of the body portion and through the barrier layer and a portion of the channel layer.
    Type: Application
    Filed: September 23, 2020
    Publication date: February 17, 2022
    Inventors: Chih-Tung Yeh, Chun-Liang Hou, Wen-Jung Liao, Chun-Ming Chang, Yi-Shan Hsu, Ruey-Chyr Lee