Abstract: An optical intraocular pressure measuring apparatus includes a light source, an optical module, a pressure providing module, a deformation measuring module, and a processing module. The light source provides an incident light. The optical module divides the incident light into a first incident light and a second incident light and emits them to a reference object and an object to be detected through a first light path and a second light path, and receives a first reflected light signal from reference object and a second reflected light signal from the object to be detected respectively. The pressure providing module coupled with second light path provides a pressure to deform the object to be detected. The deformation measuring module measures the deformation of the object to be detected. The processing module processes the first reflected light signal and second reflected light signal to generate an intraocular pressure measurement result.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate, a channel layer, a gate insulation layer, a source, a drain and a silicon-aluminum-oxide layer. The gate is disposed on a substrate. The channel layer is disposed on the substrate. The channel layer overlaps the gate. The gate insulation layer is disposed between the gate and the channel layer. The source and the drain are disposed on two sides of the channel layer. The silicon-aluminum-oxide layer is disposed on the substrate and covers the source, the drain and the channel layer.

Abstract: An active device including a source, a drain, an oxide semiconductor layer, a gate and a gate insulator layer is provided. The source includes first stripe electrodes parallel to each other and a first connection electrode connected thereto. The drain includes second stripe electrodes parallel to each other and a second connection electrode connected thereto, wherein the first stripe electrodes and the second stripe electrodes are parallel to each other, electrically isolated, and alternately arranged, and a zigzag trench is formed therebetween. The gate extends along the zigzag trench. The oxide semiconductor layer is in contact with the source and drain, wherein a contact area among the oxide semiconductor layer and each first stripe electrodes substantially equals to a layout area of each first stripe electrodes and a contact area among each second stripe electrodes substantially equals to a layout area of each second stripe electrodes.

Abstract: A simplified and cost-effective three-axis positioning device and method for ophthalmic examination instrument is disclosed. The three-axis positioning device includes an illuminating optical path for projecting light to illuminate an examinee's fundus; an imaging optical path including an objective lens for receiving the examinee's fundus image and light reflected from the examinee's cornea and eye-lens; a software-based alignment module for determining intensity and position of the reflected light on the fundus image to generate auxiliary positioning information; and an image displaying unit for showing the fundus image, the reflected light, and the auxiliary positioning information. From the intensity and position of the reflected light, x-, y- and z-axis relative positions between the examinee's pupil and the objective lens are obtained. An examiner adjusts the relative positions in three axes until they fall within an allowable deviation range, and a clear fundus image can be obtained.

Abstract: The present invention is correlated with a derivative of 18?-glycyrrhetinic acid apt to suppressing cancer cells, which is selected from a group comprising of structure I and structure II: wherein residue R1 is selected from one of CH3 and CH2C6H5, residue R2 is selected from one of COOCH3, COOCH2CH3, COOCH(CH3)2, CONHCH2CH3, CONHCH2CH2CH3, and CONHCH2(CH3)2, and residue R3 is selected from one of COOCH2CH3, COOCH(CH3)2, CONHCH2CH3, CONHCH2CH2CH3, and CONHCH2(CH3)2.

Abstract: A semiconductor device structure on a substrate and a manufacture method thereof is provided. The semiconductor device structure includes an oxide semiconductor transistor and a passivation layer containing free hydrogen. The semiconductor device structure is formed by following steps. A gate electrode is formed on the substrate. A gate dielectric layer covers the gate electrode. A source electrode is formed on the gate dielectric layer. A drain electrode is formed on the gate dielectric layer and separated from the source electrode and thereby forming a channel distance. An oxide semiconductor layer is formed on the gate dielectric layer, the source electrode and the drain electrode and between the source electrode and the drain electrode. The oxide semiconductor layer is further electrically connected with the source electrode and the drain electrode. A passivation layer covers the oxide semiconductor layer, the source electrode and the drain electrode.

Abstract: The present invention provides a network unit replacing method for an embedded system device having an internal network unit and a related embedded system device. The network unit replacing method comprises: detecting a network unit type of the embedded system device, to generate a detecting result; and when the detecting result indicates that the embedded system device has at least an external network unit currently, initializing the external network unit to make the embedded system device access network via the external network unit instead of the internal network unit.

Abstract: The present invention provides a chemical compound having the structure being one selected from a group consisting of wherein R1 is one selected from a group consisting of COOCH3, COOCH2Ph, CONHCH(CH3)2 and CONHC6H5, R2 is one selected from a group consisting of H, CH3 and CH(CH3)2, R3 is one selected from a group consisting of H, CH3, CH(CH3)2 and CH2Ph, and R4 is one of CH(CH3)2 and C6H5.

Abstract: A fabricating method of an active device array substrate is provided. The active device array substrate has at least one patterned conductive layer. The patterned conductive layer includes a copper layer. A cross-section of the copper layer which is parallel to a normal line direction of the copper layer includes a first trapezoid and a second trapezoid stacked on the first trapezoid. A base angle of the first trapezoid and a base angle of the second trapezoid are acute angles, and a difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5° to about 30°.

Abstract: A pixel structure disposed on a substrate including a thin film transistor (TFT), a passivation layer, and a pixel electrode is provided. The TFT includes a gate, a dielectric layer, a channel layer, and a source/drain sequentially disposed on the substrate. The source/drain is disposed on a portion of the channel layer and has a semiconductor layer, a barrier layer and a metal layer. The barrier layer is disposed on a portion of the semiconductor layer. The metal layer is disposed on the barrier layer. The barrier layer is in contact with the semiconductor layer and the metal layer. Both of the metal layer and the barrier layer are positioned within a projection area of the semiconductor layer. The passivation layer covers the TFT and the dielectric layer and has a first opening exposing the source/drain. The pixel electrode is electrically connected to the TFT through the first opening.

Abstract: An active device array substrate has at least one patterned conductive layer. The patterned conductive layer includes a copper layer. A cross-section of the copper layer which is parallel to a normal line direction of the copper layer includes a first trapezoid and a second trapezoid stacked on the first trapezoid. A base angle of the first trapezoid and a base angle of the second trapezoid are acute angles, and a difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5° to about 30°.

Abstract: A pixel structure disposed on a substrate including a thin film transistor (TFT), a bottom capacitor electrode, a dielectric layer, an upper capacitor electrode, a passivation layer, and a pixel electrode is provided. The TFT having a source/drain and the bottom capacitor electrode are disposed on the substrate. The dielectric layer is disposed on the bottom capacitor electrode. The upper capacitor electrode has a semiconductor layer, a barrier layer, and a metal layer. The semiconductor layer is disposed on the dielectric layer above the bottom capacitor electrode. The barrier layer is disposed on the semiconductor layer. The metal layer whose material includes copper, a copper alloy, or a combination thereof is disposed on the barrier layer. The passivation layer covers the TFT and the upper capacitor electrode and has a first opening exposing the source/drain. The pixel electrode is electrically connected to the TFT through the first opening.

Abstract: Disclosed are a serious of 2?,5?-dimethoxychalcone derivatives for treating cancer, wherein 2,5-dimethoxyacetophenone and methyl 4-formylbenzoate are condensed to form 4-carboxyl-2?,5?-dimethoxychalcone (compound 1), which is further reacted with alkyl halides or amines to synthesize the chalcone derivatives of compounds 2-17. In addition, 2,5-dimethoxyacetophenone is reacted with 5-formyl-2-thiophenecarboxylic acid to form compound 18 (3-(3-thiophene)carboxyl-1-(2,5-dimethoxyphenyl)prop-2-en-1-one). The synthesized 2?,5?-dimethoxychalcone derivatives can be acted as microtubule-targeted tubulin-polymerizing agents.

Abstract: A display panel structure having a circuit element disposed thereon and method of manufacture are provided. The display panel includes a substrate and the circuit element disposed on the substrate. The circuit element has a first interface layer and a first conductive layer. Both the first interface layer and the first conductive layer have cooper materials. The material which makes the first interface layer includes a reactant or a compound of the material which makes the first conductive layer. The method for manufacturing includes the following steps: forming a first interface layer on the substrate; forming a first conductive layer on the first interface layer; and etching the first conductive and interface layers to form a pattern. The existence of the first interface reduces the penetration of the first conductive layer on the substrate and improves the adhesive force between the first conductive layer and the substrate.

Abstract: An active device array substrate has at least one patterned conductive layer. The patterned conductive layer includes a copper layer. A cross-section of the copper layer which is parallel to a normal line direction of the copper layer includes a first trapezoid and a second trapezoid stacked on the first trapezoid. A base angle of the first trapezoid and a base angle of the second trapezoid are acute angles, and a difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5° to about 30°.

Abstract: Several ursolic acid derivatives and pharmaceutical compositions thereof are provided. The ursolic acid derivatives and the pharmaceutical compositions thereof have at least one of an anticancer and an anti-inflammatory effects. A method for increasing a reactive oxygen species in a cell is also provided. The method comprises a step of providing the cell with a pharmaceutical composition including an ursolic acid derivative.

Abstract: A semiconductor device structure on a substrate and a manufacture method thereof is provided. The semiconductor device structure includes an oxide semiconductor transistor and a passivation layer containing free hydrogen. The semiconductor device structure is formed by following steps. A gate electrode is formed on the substrate. A gate dielectric layer covers the gate electrode. A source electrode is formed on the gate dielectric layer. A drain electrode is formed on the gate dielectric layer and separated from the source electrode and thereby forming a channel distance. An oxide semiconductor layer is formed on the gate dielectric layer, the source electrode and the drain electrode and between the source electrode and the drain electrode. The oxide semiconductor layer is further electrically connected with the source electrode and the drain electrode. A passivation layer covers the oxide semiconductor layer, the source electrode and the drain electrode.

Abstract: A display panel structure having a circuit element disposed thereon and method of manufacture are provided. The display panel includes a substrate and the circuit element disposed on the substrate. The circuit element has a first interface layer and a first conductive layer. Both the first interface layer and the first conductive layer have copper materials. The material which makes the first interface layer includes a reactant or a compound of the material which makes the first conductive layer. The method for manufacturing includes the following steps: forming a first interface layer on the substrate; forming a first conductive layer on the first interface layer; and etching the first conductive and interface layers to form a pattern. The existence of the first interface reduces the penetration of the first conductive layer on the substrate and improves the adhesive force between the first conductive layer and the substrate.

Abstract: The present invention provides a chemical compound having the structure being one selected from a group consisting of wherein R1 is one selected from a group consisting of COOCH3, COOCH2Ph, CONHCH(CH3)2 and CONHC6H5, R2 is one selected from a group consisting of H, CH3 and CH(CH3)2, R3 is one selected from a group consisting of H, CH3, CH(CH3)2 and CH2Ph, and R4 is one of CH(CH3)2 and C6H5.

Abstract: A display element and a method of manufacturing the same are provided. The method comprises the following steps: forming a first patterned conducting layer with a gate on a substrate and a dielectric layer thereon; forming a patterned semiconductor layer on the dielectric layer, wherein the patterned semiconductor layer has a channel region, a source and a drain, and wherein the source and the drain lie on the opposite sides of the channel region; selectively depositing a barrier layer, which only wraps the patterned semiconductor layer; forming a second patterned conducting layer on the barrier layer and above the source and the drain. In the display element manufactured by the method, the barrier layer only wraps the patterned semiconductor layer.