Patents by Inventor Chun Ren
Chun Ren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230320227Abstract: A method for manufacturing a semiconductor structure is provided. The method may include several operations. A piezoelectric capacitor is formed over a substrate, wherein the piezoelectric capacitor includes a metal electrode. An intermediate layer is formed on the metal electrode, and is patterned using a first mask layer as a mask. A metal layer is formed on the intermediate layer, wherein the metal layer electrically connects to the metal electrode. The metal layer is patterned using a second mask layer, wherein the intermediate layer is within a coverage area of the metal layer from a top-view perspective after the patterning of the metal layer. A semiconductor structure thereof is also provided.Type: ApplicationFiled: March 29, 2022Publication date: October 5, 2023Inventors: CHING-HUI LIN, FU-CHUN HUANG, CHUN-REN CHENG, WEI CHUN WANG, CHAO-HUNG CHU, YI-HSIEN CHANG, PO-CHEN YEH, CHI-YUAN SHIH, SHIH-FEN HUANG, YAN-JIE LIAO, SHENG KAI YEH
-
Publication number: 20230302494Abstract: The present disclosure relates to an integrated chip structure. The integrated chip structure includes a dielectric stack disposed on a substrate. The integrated chip structure further includes one or more piezoelectric ultrasonic transducers (PMUTs) and one or more capacitive ultrasonic transducers (CMUTs). The one or more PMUTs include a piezoelectric stack disposed within the dielectric stack over one or more PMUT cavities. The one or more CMUTs include electrodes disposed within the dielectric stack and separated by one or more CMUT cavities. An isolation chamber is arranged within the dielectric stack laterally between the one or more PMUTs and the one or more CMUTs. The isolation chamber vertically extends past at least a part of both the one or more PMUTs and the one or more CMUTs.Type: ApplicationFiled: June 6, 2022Publication date: September 28, 2023Inventors: Ching-Hui Lin, Yi-Hsien Chang, Chun-Ren Cheng, Fu-Chun Huang, Yi Heng Tsai, Shih-Fen Huang, Chao-Hung Chu, Po-Chen Yeh
-
Patent number: 11767219Abstract: A method of fabricating a semiconductor structure includes: providing a first wafer; providing a second wafer having a first surface and a second surface opposite to the first surface; contacting the first surface of the second wafer with the first wafer; and forming a plurality of scribe lines on the second surface of the second wafer, wherein the formation of the plurality of scribe lines includes removing portions of the second wafer from the second surface towards the first surface to form a third surface between the first surface and the second surface, and the plurality of scribe lines protrudes from the third surface of the second wafer.Type: GrantFiled: July 17, 2020Date of Patent: September 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wei-Cheng Shen, Yi-Hsien Chang, Yi-Heng Tsai, Chun-Ren Cheng
-
Patent number: 11768170Abstract: A biochip including a fluidic substrate having an opening extending completely through the fluidic substrate. The biochip further includes a silicon oxide coating on the fluidic substrate. The biochip further includes a plurality of sidewalls on the fluidic substrate, wherein the plurality of sidewalls defines a channel in fluid communication with the opening, the silicon oxide coating is between adjacent sidewalls of the plurality of sidewalls, and each of the plurality of sidewalls comprises polydimethylsiloxane (PDMS). The biochip further includes a detection substrate spaced from the fluidic substrate.Type: GrantFiled: April 2, 2021Date of Patent: September 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Shao Liu, Chun-Ren Cheng, Chun-Wen Cheng
-
Publication number: 20230288369Abstract: A sensor array includes a semiconductor substrate, a first plurality of FET sensors and a second plurality of FET sensors. Each of the FET sensors includes a channel region between a source and a drain region in the semiconductor substrate and underlying a gate structure disposed on a first side of the channel region, and a dielectric layer disposed on a second side of the channel region opposite from the first side of the channel region. A first plurality of capture reagents is coupled to the dielectric layer over the channel region of the first plurality of FET sensors, and a second plurality of capture reagents is coupled to the dielectric layer over the channel region of the second plurality of FET sensors. The second plurality of capture reagents is different from the first plurality of capture reagents.Type: ApplicationFiled: April 10, 2023Publication date: September 14, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Hui LIN, Chun-Ren CHENG, Shih-Fen HUANG, Fu-Chun HUANG
-
Patent number: 11730058Abstract: In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.Type: GrantFiled: May 16, 2019Date of Patent: August 15, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Alexander Kalnitsky, Chun-Ren Cheng, Chi-Yuan Shih, Kai-Fung Chang, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yan-Jie Liao
-
Publication number: 20230240079Abstract: A semiconductor structure includes a first die, a second die, and an inter die via (IDV). The first die includes an interconnection structure and a CMOS device electrically connected to the interconnection structure. The second die includes a memory element including a first electrode, a ferroelectric layer on the first electrode, and a second electrode on the ferroelectric layer, wherein a peripheral region of the ferroelectric layer is exposed by and surrounding the second electrode from a top view perspective. The IDV electrically connects the interconnection structure of the first die to the memory element of the second die.Type: ApplicationFiled: June 7, 2022Publication date: July 27, 2023Inventors: Chun-Ren Cheng, Ching-Hui Lin, Fu-Chun Huang, Chao-Hung Chu, Po-Chen Yeh
-
Patent number: 11708262Abstract: A method of manufacturing a semiconductor structure includes following operations. A first substrate is provided. A plate is formed over the first substrate. The plate includes a first tensile member, a second tensile member, a semiconductive member between the first tensile member and the second tensile member, and a plurality of apertures penetrating the first tensile member, the semiconductive member and the second tensile member. A membrane is formed over and separated from the plate. The membrane include a plurality of holes. A plurality of conductive plugs passing through the plate or membrane are formed. A plurality of semiconductive pads are formed over the plurality of conductive plugs. The plate is bonded to a second substrate. The second substrate includes a plurality of bond pads, and the semiconductive pads are in contact with the bond pads.Type: GrantFiled: March 4, 2022Date of Patent: July 25, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yi-Hsien Chang, Chun-Ren Cheng, Wei-Cheng Shen, Wen-Chien Chen
-
Patent number: 11702691Abstract: An integrated semiconductor device for manipulating and processing bio-entity samples and methods are described. The device includes a lower substrate, at least one optical signal conduit disposed on the lower substrate, at least one cap bonding pad disposed on the lower substrate, a cap configured to form a capped area, and disposed on the at least one cap bonding pad, a fluidic channel, wherein a first side of the fluidic channel is formed on the lower substrate and a second side of the fluidic channel is formed on the cap, a photosensor array coupled to sensor control circuitry, and logic circuitry coupled to the fluidic control circuitry, and the sensor control circuitry.Type: GrantFiled: December 3, 2020Date of Patent: July 18, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Allen Timothy Chang, Yi-Hsien Chang, Chun-Ren Cheng
-
Patent number: 11703475Abstract: A method includes mounting an integrated electro-microfluidic probe card to a device area on a bio-sensor device wafer, wherein the electro-microfluidic probe card has a first major surface and a second major surface opposite the first major surface. The method further includes electrically connecting at least one electronic probe tip extending from the first major surface to a corresponding conductive area of the device area. The method further includes stamping a test fluid onto the device area. The method further includes measuring via the at least one electronic probe tip a first electrical property of one or more bio-FETs of the device area based on the test fluid.Type: GrantFiled: September 30, 2019Date of Patent: July 18, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Shao Liu, Fei-Lung Lai, Chun-Ren Cheng, Chun-Wen Cheng
-
Patent number: 11624726Abstract: A sensor array includes a semiconductor substrate, a first plurality of FET sensors and a second plurality of FET sensors. Each of the FET sensors includes a channel region between a source and a drain region in the semiconductor substrate and underlying a gate structure disposed on a first side of the channel region, and a dielectric layer disposed on a second side of the channel region opposite from the first side of the channel region. A first plurality of capture reagents is coupled to the dielectric layer over the channel region of the first plurality of FET sensors, and a second plurality of capture reagents is coupled to the dielectric layer over the channel region of the second plurality of FET sensors. The second plurality of capture reagents is different from the first plurality of capture reagents.Type: GrantFiled: March 22, 2021Date of Patent: April 11, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Hui Lin, Chun-Ren Cheng, Shih-Fen Huang, Fu-Chun Huang
-
Publication number: 20230081170Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.Type: ApplicationFiled: October 31, 2022Publication date: March 16, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Alexander KALNITSKY, Yi-Shao LIU, Kai-Chih LIANG, Chia-Hua CHU, Chun-Ren CHENG, Chun-Wen CHENG
-
Patent number: 11588095Abstract: In some embodiments, a piezoelectric biosensor is provided. The piezoelectric biosensor includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A sensing reservoir is disposed over the piezoelectric structure and exposed to an ambient environment, where the sensing reservoir is configured to collect a fluid comprising a number of bio-entities.Type: GrantFiled: May 24, 2019Date of Patent: February 21, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Hui Lin, Chun-Ren Cheng, Shih-Fen Huang, Fu-Chun Huang
-
Patent number: 11581308Abstract: A method for manufacturing a semiconductor structure is provided, wherein the method includes the following operations. A substrate having a transistor is received, wherein the transistor includes a channel region and a gate on a first side of the channel region. A second side of the channel region of the transistor is exposed, wherein the second side is opposite to the first side. A metal oxide is formed on the second side of the channel region of the transistor, wherein the metal oxide contacts the channel region and is exposed to the environment. A semiconductor structure and an operation of a semiconductor structure thereof are also provided.Type: GrantFiled: July 8, 2020Date of Patent: February 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Fu-Chun Huang, Ching-Hui Lin, Chun-Ren Cheng, Shih-Fen Huang, Alexander Kalnitsky
-
Patent number: 11543862Abstract: A hinge mechanism includes a hinge assembly connected with a first body and a second body to rotatably connect the first body and the second body, and a torque assembly mounted at the first body and connected with the hinge assembly. When the first body and the second body are relatively rotated to drive the hinge assembly, the hinge assembly drives the torque assembly to cause at least a part of the torque assembly to translate relative to the first body to provide a torque for the hinge assembly.Type: GrantFiled: March 19, 2021Date of Patent: January 3, 2023Assignee: LENOVO (BEIJING) CO., LTD.Inventor: Chun Ren
-
Publication number: 20220384709Abstract: In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.Type: ApplicationFiled: August 5, 2022Publication date: December 1, 2022Inventors: Alexander Kalnitsky, Chun-Ren Cheng, Chi-Yuan Shih, Kai-Fung Chang, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yan-Jie Liao
-
Publication number: 20220376164Abstract: In some embodiments, a piezoelectric biosensor is provided. The piezoelectric biosensor includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A sensing reservoir is disposed over the piezoelectric structure and exposed to an ambient environment, where the sensing reservoir is configured to collect a fluid comprising a number of bio-entities.Type: ApplicationFiled: August 4, 2022Publication date: November 24, 2022Inventors: Ching-Hui Lin, Chun-Ren Cheng, Shih-Fen Huang, Fu-Chun Huang
-
Patent number: 11508902Abstract: A method of manufacturing a semiconductor device includes: forming a first substrate includes a membrane stack over a first dielectric layer, the membrane stack having a first electrode, a second electrode over the first electrode and a piezoelectric layer between the first electrode and the second electrode, a third electrode over the first dielectric layer, and a second dielectric layer over the membrane stack and the third electrode; forming a second substrate, including: a redistribution layer (RDL) over a third substrate, the RDL having a fourth electrode; and a first cavity on a surface of the RDL adjacent to the fourth electrode; forming a second cavity in one of the first substrate and the second substrate; and bonding the first substrate to the second substrate.Type: GrantFiled: March 5, 2021Date of Patent: November 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yi Heng Tsai, Fu-Chun Huang, Ching-Hui Lin, Chun-Ren Cheng
-
Patent number: 11486854Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.Type: GrantFiled: December 26, 2019Date of Patent: November 1, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Alexander Kalnitsky, Yi-Shao Liu, Kai-Chih Liang, Chia-Hua Chu, Chun-Ren Cheng, Chun-Wen Cheng
-
Patent number: 11466164Abstract: An electrocoat system for electrodeposition is described. The system includes an inorganic bismuth-containing compound or a mixture of inorganic and organic bismuth-containing compounds. The system demonstrates a high degree of crosslinking and produces a cured coating with optimal crosslinking and corrosion resistance.Type: GrantFiled: April 6, 2020Date of Patent: October 11, 2022Assignee: The Sherwin-Williams CompanyInventors: Victoria J. Gelling, Tapan DebRoy, Chun Ren