Abstract: A memory device includes a base die configured to transmit transmission data that are driven to a first voltage range through a transmission line based on base data, and a core die configured to generate core data by shifting a voltage level of the transmission data received through the transmission line to a second voltage range.

Abstract: A processing-in-memory (PIM) device includes a multiplication-and-accumulation (MAC) circuit, a memory circuit, and an address pipeline circuit. The MAC circuit is configured to perform a MAC arithmetic operation or an element-wise multiplication (EWM) calculation for first input data and second input data to generate result data. The memory circuit is configured to output the first input data and the second input data to the MAC circuit in response to a read control signal and is configured to store the result data in response to a write control signal. The address pipeline circuit is configured to receive the read control signal to store an address signal used as a target address signal for designating a region of the memory circuit into which the result data are stored. In addition, the address pipeline circuit is configured to receive the write control signal to output the target address signal to the memory circuit.

Abstract: A processing-in-memory (PIM) device includes a multiplication-and-accumulation (MAC) circuit, a memory circuit, and an address pipeline circuit. The MAC circuit is configured to perform a MAC arithmetic operation or an element-wise multiplication (EWM) calculation for first input data and second input data to generate result data. The memory circuit is configured to output the first input data and the second input data to the MAC circuit in response to a read control signal and is configured to store the result data in response to a write control signal. The address pipeline circuit is configured to receive the read control signal to store an address signal used as a target address signal for designating a region of the memory circuit into which the result data are stored. In addition, the address pipeline circuit is configured to receive the write control signal to output the target address signal to the memory circuit.

Abstract: In accordance with an embodiment of the present disclosure, an image synchronization device includes a light emitting source configured to emit light at intervals of a predetermined time, a sampling phase calibration circuit configured to calibrate a sampling phase of each of the first image sensor and the second image sensor on the basis of a light emitting timing of the light emitting source and a delay calibration circuit configured to generate delay information on the basis of a result of comparison between first image information transmitted from the first image sensor and second image information transmitted from the second image sensor.

Abstract: In accordance with an embodiment of the present disclosure, a semiconductor system includes a first semiconductor device coupled to a first transmission line, and configured to transmit a first packet to a second transmission line on the basis of first destination information of the first packet received through the first transmission line; a second semiconductor device coupled to the first semiconductor device through the second transmission line, and configured to transmit a second packet to a third transmission line on the basis of second destination information of the second packet received through the second transmission line; and a third semiconductor device coupled to the second semiconductor device through the third transmission line, coupled to the first semiconductor device through the first transmission line, and configured to transmit a third packet to the first transmission line on the basis of third destination information of the third packet received through the third transmission line.

Abstract: A processing-in-memory (PIM) device includes a multiplier circuit, a memory circuit, and an address pipeline circuit. The multiplier circuit is configured to perform an element-wise multiplication (EWM) calculation of first input data and second input data to generate result data. The memory circuit is configured to output the first input data and the second input data to the multiplier circuit in response to a read control signal and is configured to store the result data in response to a write control signal. The address pipeline circuit is configured to receive the read control signal to store an address signal used as a target address signal for designating a region of the memory circuit into which the result data are stored. In addition, the address pipeline circuit is configured to receive the write control signal to output the target address signal to the memory circuit.

Abstract: A processing-in-memory (PIM) device includes a multiplier circuit, a memory circuit, and an address pipeline circuit. The multiplier circuit is configured to perform an element-wise multiplication (EWM) calculation of first input data and second input data to generate result data. The memory circuit is configured to output the first input data and the second input data to the multiplier circuit in response to a read control signal and is configured to store the result data in response to a write control signal. The address pipeline circuit is configured to receive the read control signal to store an address signal used as a target address signal for designating a region of the memory circuit into which the result data are stored. In addition, the address pipeline circuit is configured to receive the write control signal to output the target address signal to the memory circuit.

Abstract: In accordance with an embodiment of the present disclosure, an image synchronization device includes a light emitting source configured to emit light at intervals of a predetermined time, a sampling phase calibration circuit configured to calibrate a sampling phase of each of the first image sensor and the second image sensor on the basis of a light emitting timing of the light emitting source and a delay calibration circuit configured to generate delay information on the basis of a result of comparison between first image information transmitted from the first image sensor and second image information transmitted from the second image sensor.

Abstract: In accordance with an embodiment of the present disclosure, a semiconductor system includes a first semiconductor device coupled to a first transmission line, and configured to transmit a first packet to a second transmission line on the basis of first destination information of the first packet received through the first transmission line; a second semiconductor device coupled to the first semiconductor device through the second transmission line, and configured to transmit a second packet to a third transmission line on the basis of second destination information of the second packet received through the second transmission line; and a third semiconductor device coupled to the second semiconductor device through the third transmission line, coupled to the first semiconductor device through the first transmission line, and configured to transmit a third packet to the first transmission line on the basis of third destination information of the third packet received through the third transmission line.

Abstract: A stacked memory device includes: a plurality of semiconductor chips that are stacked and transfer signals through a plurality of through-electrodes, wherein at least one of the semiconductor chips comprises: a re-timing circuit suitable for receiving input signals and first and second clocks, performing a re-timing operation of latching the input signals based on the second clock to output re-timed signals, and reflecting a delay time of the re-timing operation into the first clock to output a replica clock; and a transfer circuit suitable for transferring the re-timed signals to the through-electrodes based on the replica clock.

Abstract: A memory system and a method for operating the same, wherein the memory system includes a first memory and a second memory each configured to store data. The memory system further includes a test and repair circuit operationally connected to the first memory and to the second memory. The test and repair circuit is configured to receive a test initiation signal and perform, in response to receiving the test initiation signal, a test operation on at least one of the first memory and the second memory. The test and repair circuit is also configured to perform, based on a result of the test operation, a repair operation on the at least one of the first memory and the second memory.

Abstract: A stacked memory device includes: a plurality of semiconductor chips that are stacked and transfer signals through a plurality of through-electrodes, wherein at least one of the semiconductor chips comprises: a re-timing circuit suitable for receiving input signals and first and second clocks, performing a re-timing operation of latching the input signals based on the second clock to output re-timed signals, and reflecting a delay time of the re-timing operation into the first clock to output a replica clock; and a transfer circuit suitable for transferring the re-timed signals to the through-electrodes based on the replica clock.

Abstract: A memory system and a method for operating the same, wherein the memory system includes a first memory and a second memory each configured to store data. The memory system further includes a test and repair circuit operationally connected to the first memory and to the second memory. The test and repair circuit is configured to receive a test initiation signal and perform, in response to receiving the test initiation signal, a test operation on at least one of the first memory and the second memory. The test and repair circuit is also configured to perform, based on a result of the test operation, a repair operation on the at least one of the first memory and the second memory.

Abstract: A semiconductor apparatus includes a direct access section, an interface section, and a through-via region. The direct access section receives first and second groups of input signals through a direct access pad, and generates first and second groups of control signals based on the first and second groups of input signals. The interface section comprises a plurality of channel circuits suitable for receiving a part or all of the first and second groups of control signals in response to a plurality of channel selection signals. The through-via region electrically couples the plurality of channel circuits and a plurality of stack dies to form a plurality of channels, respectively.

Abstract: A signal shifting circuit may include a bank selection signal generation unit suitable for generating a bank selection signal synchronized with a first clock in response to a bank address and an internal write signal; and a shifting device suitable for generating a shifted bank selection signal by shifting the bank selection signal by a number of times according to latency information and for advancing a phase of the shifted bank selection signal whenever shifting the bank selection signal once or more so that the shifted bank selection signal is synchronized with a second clock having a phase leading a phase of the first clock.

Abstract: A base chip including first to Nth delay units coupled in series, where N is a natural number equal to or larger than 2, wherein when the number of stacked chips over the base chip is 1, the base chip is suitable for delaying a refresh signal, and generating first to Xth delayed refresh signals using the first to Xth delay units among the first to Nth delay units, where X is a natural number having a relation of N>X?1, and when the number of stacked chips over the base chip is 2, the base chip is suitable for delaying the refresh signal, and generating first to Yth delayed refresh signals using the first to Yth delay units among the first to Nth delay units, where Y is a natural number having a relation of N?Y>X.

Abstract: A latch circuit may be provided. The latch circuit may include a plurality of latches configured to store and output data through input/output signal lines according to input/output control signals. Latches coupled with input/output signal lines of same orders among the plurality of latches may be disposed by being distributed by orders of the input/output control signals. A plurality of pipe latches may be configured by latches which are inputted with input/output control signals of same orders, among the latches disposed by being distributed.

Abstract: A latch circuit may be provided. The latch circuit may include a plurality of latches configured to store and output data through input/output signal lines according to input/output control signals. Latches coupled with input/output signal lines of same orders among the plurality of latches may be disposed by being distributed by orders of the input/output control signals. A plurality of pipe latches may be configured by latches which are inputted with input/output control signals of same orders, among the latches disposed by being distributed.

Abstract: A signal shifting circuit may include a bank selection signal generation unit suitable for generating a bank selection signal synchronized with a first clock in response to a bank address and an internal write signal; and a shifting device suitable for generating a shifted bank selection signal by shifting the bank selection signal by a number of times according to latency information and for advancing a phase of the shifted bank selection signal whenever shifting the bank selection signal once or more so that the shifted bank selection signal is synchronized with a second clock having a phase leading a phase of the first clock.

Abstract: A base chip including first to Nth delay units coupled in series, where N is a natural number equal to or larger than 2, wherein when the number of stacked chips over the base chip is 1, the base chip is suitable for delaying a refresh signal, and generating first to Xth delayed refresh signals using the first to Xth delay units among the first to Nth delay units, where X is a natural number having a relation of N>X?1, and when the number of stacked chips over the base chip is 2, the base chip is suitable for delaying the refresh signal, and generating first to Yth delayed refresh signals using the first to Yth delay units among the first to Nth delay units, where Y is a natural number having a relation of N?Y>X.