Abstract: A semiconductor memory device includes an operation control block suitable for controlling an entrance/escape to/from a test public mode and a test application mode in response to a first preset command and an address signal that is inputted through an address pad, a test normal input block suitable for receiving the address signal as a test operation signal in response to the first preset command in the test application mode, a test public input block suitable for receiving a data signal, which is inputted through a data pad as the test operation signal in response to a second preset command in the test public mode, and an internal circuit suitable for performing a preset test operation in response to the test operation signal in the test application mode.

Abstract: A semiconductor apparatus includes a through via and a comparison unit. The through via is electrically connected with another chip. The comparison unit includes a reference capacitor, and compares a capacitance value of the through via and a capacitance value of the reference capacitor in response to a test start signal and a reset signal and generates a comparison result.

Abstract: An on die thermal sensor (ODTS) of a semiconductor memory device includes a high voltage generating unit for generating a high voltage having a voltage level higher than that of a power supply voltage of the semiconductor memory device; and a thermal information output unit for sensing and outputting a temperature as a thermal information code, wherein the thermal information output unit uses the high voltage as its driving voltage.

Abstract: A memory device includes a memory array suitable for storing write data of the memory device and providing the stored data as read data of the memory device, a programmable storage unit suitable for storing information for the memory device, a command decoder suitable for storing decoding one or more command signals, and generating a write command for writing the write data, a read command for outputting the read data, and an information read command for outputting information stored in the programmable storage unit, a control unit suitable for controlling the information stored in the programmable storage unit to be sequentially read in response to activation of the information read command, and an output unit suitable for outputting the read information to an outside of the memory device in response to the information read command.

Abstract: A semiconductor device includes a plurality of stacked chips, a reference through silicon via (TSV) set passing through the plurality of stacked chips, a plurality of TSVs passing through the plurality of stacked chips, a reference delay information generation unit suitable for generating a reference delay information indicating an amount of delay of the reference TSV set and a determination unit suitable for determining abnormality of the plurality of TSVs by comparing a first test signal with each of a plurality of second test signals, wherein the first test signal is an initial test signal delayed by an amount of delay corresponding to the reference delay information, and wherein each of the plurality of second test signals is the initial test signal delayed by corresponding one of the plurality of TSVs.

Abstract: A signal transmission circ it includes a main driving unit configured to drive a first signal transmission One in response to an input signal and output a first driven signal, an emphasis driving unit configured to perform an emphasis operation on the first driven signal and output an emphasized signal, and a crosstalk control unit configured to perform an equalizing operation on the emphasized signal.

Abstract: A phase detector includes a phase comparing circuit configured to detect and output a phase difference between a first clock signal and a second clock signal, a latch circuit configured to latch an output signal of the phase comparing circuit and output a phase detection signal, and an initial voltage control circuit configured to control an initial voltage of an input terminal of the latch circuit according to a control signal.

Abstract: A semiconductor integrated circuit includes a plurality of semiconductor chips stacked in a multi-layer structure; a correction circuit in each semiconductor chip configured to reflect a delay time corresponding to the position of the chip in the stack into an input signal to output to each semiconductor chip; and a plurality of through-chip vias formed vertically through each of the semiconductor chips and configured to transmit the input signal to the semiconductor chip.

Abstract: A semiconductor memory system configured to exchange signals through channels may include a memory control device configured to have a plurality of channels, a plurality of memory devices configured to be connected to each of the plurality of channels, wherein the plurality of channels share at least one of the plurality of memory devices.

Abstract: A pipe latch control circuit and a semiconductor integrated circuit using the same are provided. The pipe latch control circuit includes a read command control unit that receives a first signal and generates a read signal in response to a control signal. In the pipe latch control circuit, the read command control unit selects, in response to the control signal, the first signal or selects a second signal obtained by delaying the first signal according to an internal clock, and generates the selected first or second signal as the read signal.

Abstract: A multi-chip package system includes a signal transmission line commonly coupled to a plurality of semiconductor chips to transfer data to/from the semiconductor chips from/to outside; and a termination controller suitable for detecting a loading value of the signal transmission line and controlling a termination operation on the signal transmission line based on the loading value.

Abstract: A semiconductor integrated circuit includes a plurality of semiconductor chips stacked in a multi-layer structure; a correction circuit in each semiconductor chip configured to reflect a delay time corresponding to the position of the chip in the stack into an input signal to output to each semiconductor chip; and a plurality of through-chip vias formed vertically through each of the semiconductor chips and configured to transmit the input signal to the semiconductor chip.

Abstract: A multi-chip system may include a plurality of chips, and a channel shared by the plurality of chips. At least one of the plurality of chips includes a transmission circuit configured to transmit a signal to the channel. Drivability of the transmission circuit is adjusted based on a number of the plurality of chips.

Abstract: A data equalizing circuit includes an equalizer configured to output data according to a control code; and a detection unit configured to divide the data into N number of calculation periods, count data transition frequencies for the N calculation periods, calculate dispersion values of the data transition frequencies for the N calculation periods, and output the control code corresponding to a largest dispersion value, in response to a counting interruption signal and a counting completion signal, wherein n is equal to or greater than 2, N is greater than n, and the data is divided to n number of unit intervals (UI), and wherein a phase shift of each of the calculation periods with respect to its corresponding UI is different from a phase shift of any of the other calculation periods with respect to its corresponding UI.

Abstract: A semiconductor apparatus includes a TSV formed to be electrically connected with another chip and a TSV test unit configured to check a capacitance component of the TSV to generate a TSV abnormality signal.

Abstract: A signal transmission circ it includes a main driving unit configured to drive a first signal transmission One in response to an input signal and output a first driven signal, an emphasis driving unit configured to perform an emphasis operation on the first driven signal and output an emphasized signal, and a crosstalk control unit configured to perform an equalizing operation on the emphasized signal.

Abstract: A semiconductor memory system configured to exchange signals through channels may include a memory control device configured to have a plurality of channels, a plurality of memory devices configured to be connected to each of the plurality of channels, wherein the plurality of channels share at least one of the plurality of memory devices.

Abstract: A multi-chip system may include a plurality of chips, and a channel shared by the plurality of chips. At least one of the plurality of chips includes a transmission circuit configured to transmit a signal to the channel. Drivability of the transmission circuit is adjusted based on a number of the plurality of chips.

Abstract: A semiconductor apparatus includes a chip containing a plurality of through-vias, a test voltage input unit, and a test result reception unit. The test voltage input unit applies a test voltage to one of the plurality of through-vias. The test result reception unit receives an output signal outputted from one or more of the plurality of through-vias.

Abstract: A signal transmission circuit may include a main driving unit configured to drive a first signal transmission line with given driving force in response to a first input signal, and a crosstalk cancellation unit configured to differentiate a signal transferred through a second signal transmission line, which is adjacent to the first signal transmission line, and incorporate a differentiated value into the first signal transmission line.