Patents by Inventor Chun-Te Lee

Chun-Te Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11916314
    Abstract: A mobile device includes a housing, a first radiation element, a second radiation element, a third radiation element, a first switch element, and a second switch element. The first radiation element has a first feeding point. The second radiation element has a second feeding point. The first radiation element, the second radiation element, and the third radiation element are distributed over the housing. The first switch element is closed or open, so as to selectively couple the first radiation element to the third radiation element. The second switch element is closed or open, so as to selectively couple the second radiation element to the third radiation element. An antenna structure is formed by the first radiation element, the second radiation element, and the third radiation element.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: February 27, 2024
    Assignee: HTC Corporation
    Inventors: Cheng-Hung Lin, Szu-Po Wang, Chia-Te Chien, Chun-Chieh Wang, Kang-Ling Li, Chun-Hsien Lee, Yu-Chieh Chiu
  • Publication number: 20240014118
    Abstract: In a flip chip package, lines, an identification line and a dummy line are provided on a first surface of a light-transmissive carrier, and a supportive layer is disposed on a second surface of the light-transmissive carrier. Bumps and an identification bump of a chip are bonded to the lines and the identification line, respectively. Shadows of the dummy line, the identification line and the identification bump which are projected on the second surface are visible from an opening of the supportive layer. The shadows can be inspected through the opening so as to know whether the bumps are bonded to the lines correctly.
    Type: Application
    Filed: June 27, 2023
    Publication date: January 11, 2024
    Inventors: Chun-Te Lee, Chih-Ming Peng, Pi-Yu Peng, Hui-Yu Huang, Yin-Chen Lin
  • Publication number: 20230380053
    Abstract: A flip-chip bonding structure includes a chip and a circuit board, the chip is bonded to the circuit board by bumps. The circuit board includes a light-transmissive substrate, a first circuit group, a second circuit group, a boundary circuit and an identifying member. The boundary circuit is located between the first and second circuit groups and projects a boundary circuit shadow on light-transmissive substrate. The boundary circuit shadow can be recognized according to the identifying member and is provided to identify the boundary between the first and second circuit groups or identify the position of leads with the smallest pitch.
    Type: Application
    Filed: April 13, 2023
    Publication date: November 23, 2023
    Inventors: Chun-Te Lee, Chih-Ming Peng, Pi-Yu Peng, Hui-Yu Huang
  • Patent number: 11792923
    Abstract: A storage device of the present invention is provided to store flexible circuit packages, each of the flexible circuit packages includes an electronic component and two circuit portions warped at both sides of the electronic component, respectively. The storage device includes a first carrier and a second carrier. The first carrier includes first accommodation elements provided for placement of the flexible circuit packages, and the second carrier includes a first press portion and a second press portion. As the second carrier is placed on the first carrier, the first and second press portions are provided to press the two circuit portions warped upwardly toward the second carrier so as to reduce the warpage of the two circuit portions.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: October 17, 2023
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Shih-Chieh Chang, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Publication number: 20230326896
    Abstract: A COF package includes a substrate and a chip, composite bumps on the chip are bonded to leads on the substrate. Each of the composite bumps includes a raising strip, a UBM layer and a bonding layer. A bonding rib is formed on the bonding layer because of the raising strip and the UBM layer, and the bonding rib on each of the composite bumps can be inserted into each of the leads and surface-contact with each of the leads to increase weld length and bonding strength between the bonding layer and the leads and further reduce a force required for bonding the chip to the substrate in a flip-chip bonding process.
    Type: Application
    Filed: February 13, 2023
    Publication date: October 12, 2023
    Inventors: Sheng-Jen Wu, Shih-Chung Chang, Hsueh-Shun Yeh, Chun-Te Lee
  • Patent number: 11764090
    Abstract: A tray includes a body for placement of a component (e.g. electronic component) and a taker disposed on a bottom surface of the body. The taker is used to take a spacer and includes a first taking element and a second taking element. The first taking element includes a first connection portion and a first confinement portion, and the second taking element includes a second connection portion and a second confinement portion. An accommodation space is provided between the first and second connection portions and a passageway is provided between the first and second confinement portions. While the spacer is moved through the passageway and into the accommodation space, it is confined in the accommodation space by the first and second confinement portions such that the taker can take away the spacer to show another tray located under the spacer as the tray is removed.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: September 19, 2023
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Hsu-Chi Lee, Pi-Yu Peng, Chun-Te Lee
  • Patent number: 11602047
    Abstract: A circuit board tape includes substrate units each including a sprocket-hole region, a layout region and a joining mark. There are odd and more than three sprocket holes on the sprocket-hole region. An imaginary line extended from the joining mark is extended to between a first layout and a second layout located on the layout region. The amount of the sprocket holes between the imaginary lines of the adjacent substrate units is odd. The circuit board tape is cut along the imaginary lines of the different substrate units so as to remove the defective substrate unit from the circuit board tape and divide the circuit board tape into a front tape and a rear tape. After joining the front and rear tapes, the region where a first layout on the front tape and a second layout on the rear tape are located is defined as a combined layout region.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: March 7, 2023
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Yin-Chen Lin, Ming-Hsiao Ke, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Publication number: 20230039895
    Abstract: A double-sided flexible circuit board includes a flexible substrate, through circuit lines, first circuit lines and second circuit lines. The first circuit lines are formed on a top surface of the flexible substrate and each includes a first segment, a bent segment and a second segment. One end of the first segment is connected to a first connection end of one of the through circuit lines. Both ends of the bent segment are connected to the other end of the first segment and one end of the second segment, respectively. A second distance between the adjacent second segments is greater than a first distance between the adjacent first segments. The second circuit lines are formed on a bottom surface of the flexible substrate and each is connected to a second connection end of one of the through circuit lines.
    Type: Application
    Filed: May 11, 2022
    Publication date: February 9, 2023
    Inventors: Yin-Chen Lin, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Publication number: 20230044473
    Abstract: A double-sided flexible circuit board includes a flexible substrate, a first circuit layer, a second circuit layer, an insulating protection layer and a plurality of through circuit lines. The first and second circuit layers are located on a top surface and a bottom surface of the flexible substrate, respectively. The insulating protection layer covers a supporting line of the second circuit layer such that the supporting line is located between the flexible substrate and the insulating protection layer. The insulating protection layer can provide electrical insulation to the supporting line of the second circuit layer to avoid short circuit conditions of the double-sided flexible circuit board during test.
    Type: Application
    Filed: June 10, 2022
    Publication date: February 9, 2023
    Inventors: Yin-Chen Lin, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Publication number: 20220328334
    Abstract: A tray includes a body for placement of a component (e.g. electronic component) and a taker disposed on a bottom surface of the body. The taker is used to take a spacer and includes a first taking element and a second taking element. The first taking element includes a first connection portion and a first confinement portion, and the second taking element includes a second connection portion and a second confinement portion. An accommodation space is provided between the first and second connection portions and a passageway is provided between the first and second confinement portions. While the spacer is moved through the passageway and into the accommodation space, it is confined in the accommodation space by the first and second confinement portions such that the taker can take away the spacer to show another tray located under the spacer as the tray is removed.
    Type: Application
    Filed: March 9, 2022
    Publication date: October 13, 2022
    Inventors: Hsu-Chi Lee, Pi-Yu Peng, Chun-Te Lee
  • Publication number: 20220110209
    Abstract: A storage device of the present invention is provided to store flexible circuit packages, each of the flexible circuit packages includes an electronic component and two circuit portions warped at both sides of the electronic component, respectively. The storage device includes a first carrier and a second carrier. The first carrier includes first accommodation elements provided for placement of the flexible circuit packages, and the second carrier includes a first press portion and a second press portion. As the second carrier is placed on the first carrier, the first and second press portions are provided to press the two circuit portions warped upwardly toward the second carrier so as to reduce the warpage of the two circuit portions.
    Type: Application
    Filed: September 9, 2021
    Publication date: April 7, 2022
    Inventors: Shih-Chieh Chang, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Publication number: 20220087017
    Abstract: A circuit board tape includes substrate units each including a sprocket-hole region, a layout region and a joining mark. There are odd and more than three sprocket holes on the sprocket-hole region. An imaginary line extended from the joining mark is extended to between a first layout and a second layout located on the layout region. The amount of the sprocket holes between the imaginary lines of the adjacent substrate units is odd. The circuit board tape is cut along the imaginary lines of the different substrate units so as to remove the defective substrate unit from the circuit board tape and divide the circuit board tape into a front tape and a rear tape. After joining the front and rear tapes, the region where a first layout on the front tape and a second layout on the rear tape are located is defined as a combined layout region.
    Type: Application
    Filed: July 20, 2021
    Publication date: March 17, 2022
    Inventors: Yin-Chen Lin, Ming-Hsiao Ke, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Patent number: 11234328
    Abstract: A circuit board disclosed in the present invention includes a substrate and a circuit layer. The circuit layer is formed on a surface of the substrate and includes at least one test circuit line. The test circuit line includes a main segment and a branch segment connected with each other. The branch segment is provided to be contacted with a test equipment for electrical test so as to protect the main segment from breaking during electrical test.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: January 25, 2022
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Chia-En Fan, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Patent number: 11206735
    Abstract: A flexible circuit board includes a flexible light-permeable carrier, a circuit layer, a mark and a stiffener. The circuit layer and the mark are located on a top surface of the flexible light-permeable carrier. A predetermined area and a stiffener mounting area corresponding to each other are defined on the top surface and a bottom surface of the flexible light-permeable carrier, respectively. The mark is opaque to create a shadow mark having a longitudinal reference side and a lateral reference side on the bottom surface. The stiffener is adhered to the stiffener mounting area defined on the bottom surface by aligning with the longitudinal reference side and the lateral reference side of the shadow mark.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: December 21, 2021
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Yin-Chen Lin, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Patent number: 11178756
    Abstract: A flexible circuit board includes a flexible light-permeable carrier, a circuit layer, a mark and a stiffener. The circuit layer and the mark are located on a top surface of the flexible light-permeable carrier. A predetermined area and a stiffener mounting area corresponding to each other are defined on the top surface and a bottom surface of the flexible light-permeable carrier, respectively. The mark is opaque to create a shadow mark having a longitudinal reference side and a lateral reference side on the bottom surface. The stiffener is adhered to the stiffener mounting area defined on the bottom surface by aligning with the longitudinal reference side and the lateral reference side of the shadow mark.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: November 16, 2021
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Yin-Chen Lin, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Patent number: 11177206
    Abstract: A layout structure of double-sided flexible circuit board includes a flexible substrate having a first surface and a second surface, a first circuit layer and a second circuit layer. An inner bonding region is defined on the first surface and an inner supporting region is defined on the second surface according to the inner bonding region. The first circuit layer is located on the first surface and includes first conductive lines which each includes an inner lead located on the inner bonding region. The second circuit layer is located on the second surface and includes second conductive lines which each includes an inner supporting segment located on the inner supporting region. A width difference between any two of the inner supporting segment of the second conductive lines is less than 8 ?m.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: November 16, 2021
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Chun-Te Lee, Chih-Ming Peng, Hui-Yu Huang, Yin-Chen Lin
  • Publication number: 20210267047
    Abstract: A circuit board disclosed in the present invention includes a substrate and a circuit layer. The circuit layer is formed on a surface of the substrate and includes at least one test circuit line. The test circuit line includes a main segment and a branch segment connected with each other. The branch segment is provided to be contacted with a test equipment for electrical test so as to protect the main segment from breaking during electrical test.
    Type: Application
    Filed: September 25, 2020
    Publication date: August 26, 2021
    Inventors: Chia-En Fan, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Publication number: 20210267049
    Abstract: A flexible circuit board includes a flexible light-permeable carrier, a circuit layer, a mark and a stiffener. The circuit layer and the mark are located on a top surface of the flexible light-permeable carrier. A predetermined area and a stiffener mounting area corresponding to each other are defined on the top surface and a bottom surface of the flexible light-permeable carrier, respectively. The mark is opaque to create a shadow mark having a longitudinal reference side and a lateral reference side on the bottom surface. The stiffener is adhered to the stiffener mounting area defined on the bottom surface by aligning with the longitudinal reference side and the lateral reference side of the shadow mark.
    Type: Application
    Filed: January 28, 2021
    Publication date: August 26, 2021
    Inventors: Yin-Chen Lin, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Publication number: 20210185800
    Abstract: A circuit board includes a substrate having a through hole, a circuit layer, a first measurement mark and a second measurement mark. According to the first and second measurement marks, an electronic detection device can measure a first distance between a first edge of the through hole and the first measurement mark and a second distance between a second edge of the through hole and the second measurement mark to determine whether the through hole has an undesired size or shift.
    Type: Application
    Filed: May 5, 2020
    Publication date: June 17, 2021
    Inventors: Yi-Chen Lien, Yen-Ping Huang, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Publication number: 20210159159
    Abstract: A layout structure of double-sided flexible circuit board includes a flexible substrate having a first surface and a second surface, a first circuit layer and a second circuit layer. An inner bonding region is defined on the first surface and an inner supporting region is defined on the second surface according to the inner bonding region. The first circuit layer is located on the first surface and includes first conductive lines which each includes an inner lead located on the inner bonding region. The second circuit layer is located on the second surface and includes second conductive lines which each includes an inner supporting segment located on the inner supporting region. A width difference between any two of the inner supporting segment of the second conductive lines is less than 8 ?m.
    Type: Application
    Filed: March 30, 2020
    Publication date: May 27, 2021
    Inventors: Chun-Te Lee, Chih-Ming Peng, Hui-Yu Huang, Yin-Chen Lin