Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.

Abstract: A bump of a chip package with higher bearing capacity in wire bonding is provided. The at least one bump of the chip package is a metal stacked member with a certain thickness. An overall thickness of the bump is 4.5-20 ?m. Thereby a structural strength of the bump is improved and thus able to bear positive pressure generated in wire bonding or formation of a first bonding point. Thus at least one internal circuit of a chip will not be damaged by the positive pressure and allowed to pass through an area under at least one die pad or arrange under the die pad of the chip. Thereby increased cost problem caused by internal circuit redesign of the chip can be solved and this helps to reduce cost at manufacturing end.

Abstract: A chip package with higher bearing capacity in wire bonding is provided. The chip package includes at least one conductive circuit which is a structure with a thickness ranging from 4.5 ?m to 20 ?m. Thereby a structural strength of the conductive circuit is improved and able to stand a positive pressure generated in wire bonding or formation of a first bonding point. Thus at least one internal circuit of a chip will not be damaged by the positive pressure and allowed to pass through an area under the first bonding point or arrange under the first bonding point. A problem of increased cost at manufacturing end caused by the internal circuit redesign of the chip can be solved effectively. This is beneficial to cost reduction at manufacturing end.

Abstract: A chip package and a method of manufacturing the same are provided. The chip package includes at least one insulating protective layer disposed on a periphery of a surface of a seed layer correspondingly. A plurality of insulating protective layers is arranged at the seed layer of a plurality of rectangular chips of a wafer and located corresponding to a plurality of dicing streets. Thereby cutting tools only cut the insulating protective layer, without cutting a thick metal layer during cutting process. The insulating protective layer is formed on a periphery of the thick metal layer of the chip package after the cutting process.

Abstract: A projection apparatus includes a casing, a projection lens, a first fan, a first light source module, a second light source module, a first heat dissipation module, and a second heat dissipation module. A disposing direction of the projection lens divides an accommodating space of the casing into a first region and a second region. The first fan, the first light source module, the second light source module, the first heat dissipation module, and the second heat dissipation module are located in the first region. The first heat dissipation module includes a first heat dissipation fin set and a first heat pipe. The first heat pipe is connected to the first base of the first light source module and the first heat dissipation fin set. The first heat dissipation fin set is disposed adjacent to a first air inlet, and in an axial direction of the first fan.

Abstract: A fan is provided herein, including a housing, a hub, and a plurality of blades. The housing includes a top case and a bottom case. The hub is rotatably disposed between the top case and the bottom case in an axial direction. The blades extend from the hub in a radial direction, located between the top case and the bottom case. Each of the blades has a proximal end and a distal end. The proximal end is connected to the hub. The distal end is opposite from the proximal end, located at the other side of the blade, having at least one recessed portion. Each of the recessed portions form a passage for air.

Abstract: Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.

Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.

Abstract: A semiconductor device according to the present disclosure includes a first isolation feature and a second isolation feature, a fin structure extending lengthwise along a first direction and sandwiched between the first isolation feature and the second isolation feature along a second direction perpendicular to the first direction, a first channel member disposed over the first isolation feature, a second channel member disposed over the second isolation feature, and a gate structure disposed over and wrapping around the first channel member and the second channel member.

Abstract: The present application discloses an integration package with insulating boards, which features an insulating board structure replacing a plurality of printed circuit boards and packaging materials in a conventional POP structure and comprises a base substrate, a basic circuit and at least an electronic component: the basic circuit is exposed on an upper surface of the base substrate; the electronic component and the basic circuit are electrically connected with each other; both the base substrate and the electronic component are thermally compressed and covered by a first insulating board.

Abstract: An antenna test system includes a box body, a supporting device, at least one probe device, a signal measuring device, and a moving device. The box body has at least an operation side configured to be opened to allow access to devices inside the box body. The supporting device is disposed in the box body and the antenna circuit to be tested is arranged thereon. The probe device is disposed in the box body and configured to apply an antenna testing signal to the antenna circuit to emit an antenna working signal. The signal measuring device is disposed in the box body to receive the antenna working signal emitted from the antenna circuit. The moving device is disposed in the box body and configured to carry the signal measuring device to maneuver in three directions of X-axis, Y-axis, and Z-axis to receive the antenna working signal in different positions.

Abstract: A method for manufacturing a non-volatile memory device is provided. The method includes forming a trench through a sacrificial layer and extending into a substrate, filling a first insulating material into the trench, and implanting a dopant in the first insulating material by an implantation process. Then, the first insulating material is partially removed to form a first recess between the sacrificial layers. The lowest point of the first recess is lower than the top surface of the substrate. The method includes filling a second insulating material in the first recess and removing the sacrificial layer to form a second recess adjacent to the second insulating material. The method includes forming a first polycrystalline silicon layer in the second recess, and sequentially forming a dielectric layer and a second polycrystalline silicon layer on the first polycrystalline silicon layer.

Abstract: A method of fabricating a contact structure includes the following steps. An opening is formed in a dielectric layer. A conductive material layer is formed within the opening and on the dielectric layer, wherein the conductive material layer includes a bottom section having a first thickness and a top section having a second thickness, the second thickness is greater than the first thickness. A first treatment is performed on the conductive material layer to form a first oxide layer on the bottom section and on the top section of the conductive material layer. A second treatment is performed to remove at least portions of the first oxide layer and at least portions of the conductive material layer, wherein after performing the second treatment, the bottom section and the top section of the conductive material layer have substantially equal thickness.

Abstract: A heat dissipation system suitable for a portable electronic device with two heat sources is provided. The heat dissipation system includes a fan, two heat dissipation fin sets, a gate, a first heat pipe, a second heat pipe, and a control unit. The fan is a centrifugal fan and has a main outlet and a sub outlet. The heat dissipation fin sets are disposed respectively at the main outlet and the sub outlet, and the gate is disposed at the sub outlet. The first heat pipe thermally contacts the heat sources and the heat dissipation fin set located at the main outlet. The second heat pipe thermally contacts one of the heat sources and the two heat dissipation fin sets. The control unit is electrically connected to the gate to drive the gate to open or close the sub outlet according to a load of the two heat sources.

Abstract: An optical network device includes a substrate, a photonic integrated circuit, a fiber, and a packaging cap. Photonic integrated circuit is disposed on substrate. Fiber is configured to receive a first optical signal and transmit a second optical signal. A first wavelength of first optical signal is different from a second wavelength of second optical signal. Packaging cap is configured to combine fiber with substrate, and is configured to cover photonic integrated circuit and fix fiber, so as to align fiber with photonic integrated circuit, so that an oblique angle is formed between a normal vector of a plane where photonic integrated circuit is located and a direction in which fiber extends. Photonic integrated circuit is configured to receive second optical signal according to oblique angle. Photonic integrated circuit is configured to couple first optical signal to fiber according to oblique angle.

Abstract: The embodiments of mechanisms for doping wells of finFET devices described in this disclosure utilize depositing doped films to dope well regions. The mechanisms enable maintaining low dopant concentration in the channel regions next to the doped well regions. As a result, transistor performance can be greatly improved. The mechanisms involve depositing doped films prior to forming isolation structures for transistors. The dopants in the doped films are used to dope the well regions near fins. The isolation structures are filled with a flowable dielectric material, which is converted to silicon oxide with the usage of microwave anneal. The microwave anneal enables conversion of the flowable dielectric material to silicon oxide without causing dopant diffusion. Additional well implants may be performed to form deep wells. Microwave anneal(s) may be used to anneal defects in the substrate and fins.

Abstract: A light source module including a light guide plate and a light emitting element is provided. The light guide plate includes an upper surface concentric circle structure and a lower surface concentric circle structure opposite to the upper surface concentric circle structure. The center of the upper surface concentric circle structure corresponds to the center of the lower surface concentric circle structure. The light emitting element is disposed corresponding to the center of the upper surface concentric circle structure and the center of the lower surface concentric circle structure.

Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.

Abstract: A power supply phase doubling system includes a pulse width modulation (PWM) controller and first and second phase doubling chips. The PWM controller outputs a PWM signal. The first phase doubling chip is operated at a power supply voltage and has a first PWM output pin to generate a first control signal and a second control signal according to the PWM signal, and generates a first output signal according to the first control signal. The second phase doubling chip is operated at the power supply voltage, has a second PWM output pin, and is configured to generate a second output signal according to the second control signal. The first and second phase doubling chips are respectively switched between a master mode and a slave mode according to a voltage level of the first PWM output pin and a voltage level of the second PWM output pin.

Abstract: A method for performing beamforming sounding feedback in a system-parameter-aware manner and associated apparatus are provided. The method applicable to a wireless transceiver device within a wireless communications system may include: checking a plurality of system parameters of the wireless communications system to generate a plurality of checking results of the plurality of system parameters, respectively, wherein any checking result among the plurality of checking results indicates a current value of a corresponding system parameter among the plurality of system parameters; modifying a first beamforming feedback matrix according to the plurality of checking results to generate a second beamforming feedback matrix; and sending beamforming sounding feedback information carrying the second beamforming feedback matrix to another device within the wireless communications system, for further processing of the other device.