Abstract: A lifting device of a display, is provided. The lifting device includes a stationary member, a lifting member, and an elastic module. The stationary member is suitable for being fixed to a vertical plane. The lifting member is slidably connected to the stationary member. The lifting member is suitable for being fixed to a back portion of the display. The lifting member is suitable for sliding relative to the stationary member between a first position and a second position lower than the first position. The elastic module is coupled between the stationary member and the lifting member. The elastic module is suitable for exerting a pulling force opposite to a gravity direction on the lifting member.

Abstract: A lens module includes a plurality of lenses, an annular body and a reflective element. The reflective element, the lenses and the annular are sequentially arranged along an optical axis from an object side to an image side. The lenses include a first lens that is disposed closest to the object side, and a second lens that is disposed closest to the image side. The reflective element is disposed between the object side and the first lens. The annular body is disposed between the object side and the first lens, between the lenses, or between the second lens and the image side. The lens module satisfies 0.5 mm<EPA/PL<5.5 mm where EPA is an area of an entrance pupil of the lens module, and PL is a length of the reflective element.

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.

Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

Abstract: A robot for interacting with a target object includes a robotic manipulator, a calibrating image, a camera and a processor. The robotic manipulator corresponds to a robotic manipulator coordinate. The calibrating image is disposed on the robotic manipulator. The camera corresponds to a camera coordinate and for shooting the target object and generating a picture. The processor is configured to move the robotic manipulator such that the calibrating image moves towards the target object and enters the picture. The processor records robotic manipulator coordinate datasets and camera coordinate datasets of the calibrating image as the calibrating image moving towards the target object, and uses the robotic manipulator coordinate datasets and the camera coordinate datasets to execute a hand-eye calibrating algorithm to obtain a calibrated mapping between the camera coordinate and the robotic manipulator coordinate.

Abstract: A semiconductor device includes a first polysilicon structure, wherein the first polysilicon structure has a first grain size. The semiconductor device further includes a first barrier layer over the first polysilicon structure, wherein the first barrier layer has a non-uniform thickness. The semiconductor device includes a second polysilicon structure over the first barrier layer, wherein the second polysilicon structure has a second grain size different from the first grain size.

Abstract: A multi-mode hybrid control DC-DC converting circuit has a switching power converter and a microcontroller. The switching power converter has a transformer and a switching switch. The switching switch is connected to a primary-side winding of the transformer in series. The microcontroller is connected to the switching power converter and a control terminal of the switching switch. The microcontroller sets multiple thresholds according to an input voltage of the switching power converter, and determines whether a feedback voltage of the switching power converter is higher or lower than each one of the thresholds to perform a variable-frequency mode, a constant-frequency mode, or a pulse-skipping mode. The microcontroller outputs a driving signal to the switching switch and correspondingly adjusts a frequency of the driving signal according to the variable-frequency mode, the constant-frequency mode, or the pulse-skipping mode which is performed.

Abstract: A system and method for efficiently arbitrating traffic on a bus. A computing system includes a fabric for routing traffic among one or more agents and one or more endpoints. The fabric includes multiple arbiters in an arbitration hierarchy. Arbiters store traffic in buffers with each buffer associated with a particular traffic type and a source of the traffic. Arbiters maintain a respective urgency counter for keeping track of a period of time traffic of a particular type is blocked by upstream arbiters. When the block is removed, the traffic of the particular type has priority for selection based on the urgency counter. When arbiters receive feedback from downstream arbiters or sources, the arbiters adjust selection priority accordingly. For example, changes in bandwidth requirement, low latency tolerance and active status cause adjustments in selection priority of stored requests.

Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a first polysilicon structure over the substrate, wherein the first polysilicon structure has a first grain size. The semiconductor device further includes a first barrier layer over the first polysilicon structure, wherein the first barrier layer has a non-uniform thickness. The semiconductor device further includes a second polysilicon structure over the first barrier layer, wherein the second polysilicon structure has a second grain size smaller than the first grain size.

Abstract: An electric vehicle transmission mechanism which is applied to drive a chain wheel of an electric vehicle is provided. The electric vehicle transmission mechanism includes a transmission shaft, an output shaft, a lower bearing and an upper bearing. The transmission shaft is connected to the chain wheel and has a transmission axial direction, and the transmission shaft includes a transmission portion. The output shaft includes an output portion engaged with the transmission portion, and the output shaft has an output axial direction substantially perpendicular to the transmission axial direction. The lower bearing is sleeved on the output shaft. The upper bearing is sleeved on the output shaft and located between the lower bearing and the output portion.

Abstract: An electric vehicle transmission mechanism which is applied to drive a chain wheel of an electric vehicle is provided. The electric vehicle transmission mechanism includes a transmission shaft, an output shaft, a lower bearing and an upper bearing. The transmission shaft is connected to the chain wheel and has a transmission axial direction, and the transmission shaft includes a transmission portion. The output shaft includes an output portion engaged with the transmission portion, and the output shaft has an output axial direction substantially perpendicular to the transmission axial direction. The lower bearing is sleeved on the output shaft. The upper bearing is sleeved on the output shaft and located between the lower bearing and the output portion.

Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a first polysilicon structure over the substrate, wherein the first polysilicon structure has a first grain size. The semiconductor device further includes a first barrier layer over the first polysilicon structure, wherein the first barrier layer has a non-uniform thickness. The semiconductor device further includes a second polysilicon structure over the first barrier layer, wherein the second polysilicon structure has a second grain size smaller than the first grain size.

Abstract: A system and method for efficiently arbitrating traffic on a bus. A computing system includes a fabric for routing traffic among one or more agents and one or more endpoints. The fabric includes multiple arbiters in an arbitration hierarchy. Arbiters store traffic in buffers with each buffer associated with a particular traffic type and a source of the traffic. Arbiters maintain a respective urgency counter for keeping track of a period of time traffic of a particular type is blocked by upstream arbiters. When the block is removed, the traffic of the particular type has priority for selection based on the urgency counter. When arbiters receive feedback from downstream arbiters or sources, the arbiters adjust selection priority accordingly. For example, changes in bandwidth requirement, low latency tolerance and active status cause adjustments in selection priority of stored requests.

Abstract: Embodiments relate to a denominator circuit that determines the number of valid elements of a data surface covered by a kernel depending on various locations of the kernel relative to the data surface. The denominator circuit includes a first circuit and a second circuit that have the same structure. The first circuit receives numbers representing different horizontal locations of a reference point in the kernel and generates a first matrix with first output elements corresponding to the different horizontal locations. The second circuit receives numbers representing different vertical locations of a reference point in the kernel and generates a second matrix with second output elements corresponding to the different vertical locations. A matrix multiplication of the first matrix and the second matrix is performed to obtain an array of valid elements covered by the kernel.

Abstract: Embodiments relate to a denominator circuit that determines the number of valid elements of a data surface covered by a kernel depending on various locations of the kernel relative to the data surface. The denominator circuit includes a first circuit and a second circuit that have the same structure. The first circuit receives numbers representing different horizontal locations of a reference point in the kernel and generates a first matrix with first output elements corresponding to the different horizontal locations. The second circuit receives numbers representing different vertical locations of a reference point in the kernel and generates a second matrix with second output elements corresponding to the different vertical locations. A matrix multiplication of the first matrix and the second matrix is performed to obtain an array of valid elements covered by the kernel.

Abstract: A method of making a semiconductor device includes depositing a first polysilicon layer over a substrate. The method further includes forming a barrier layer over the first polysilicon layer. The method further includes patterning the first polysilicon layer. The method further includes depositing a second polysilicon layer over the barrier layer, wherein the depositing of the second polysilicon layer includes increasing a grain size of the first polysilicon layer, and causing at least one grain boundary in the first polysilicon layer to contact the barrier layer.

Abstract: A system and method for efficiently arbitrating traffic on a bus. A computing system includes a fabric for routing traffic among one or more agents and one or more endpoints. The fabric includes multiple arbiters in an arbitration hierarchy. Arbiters store traffic in buffers with each buffer associated with a particular traffic type and a source of the traffic. Arbiters maintain a respective urgency counter for keeping track of a period of time traffic of a particular type is blocked by upstream arbiters. When the block is removed, the traffic of the particular type has priority for selection based on the urgency counter. When arbiters receive feedback from downstream arbiters or sources, the arbiters adjust selection priority accordingly. For example, changes in bandwidth requirement, low latency tolerance and active status cause adjustments in selection priority of stored requests.

Abstract: A system and method for efficiently allocating data storage to agents. A computing system includes an interconnect with intermediate buffers for storing transactions and corresponding payload data during transport between sources and destinations. A data storage limit is set on an amount of data storage corresponding to outstanding transactions for each of the multiple sources based on the initial buffer assignments. A number of outstanding transactions for each of the multiple sources is limited based on a corresponding data storage limit. If the rate of allocation of a given buffer assigned to a first source exceeds a threshold, then a second source is selected with available space exceeding a threshold in an assigned buffer. If it is determined the second source is not assigned to a buffer with a rate of allocation exceeding a threshold, then buffer storage is reassigned from the second source to the first source.

Abstract: A 3D model construction device includes a camera and a wearable display coupled to the camera. The camera obtains multiple first frames, a second frame and depth information. The wearable display includes a display unit, a processing unit, a storage unit and a projection unit. The storage unit stores a first module and a second module. When the first module is performed by the processing unit, the processing unit calculates a first pose of the wearable display. When the second module is performed by the processing unit, the processing unit calculates a 3D model according to the first frames, the depth information, the first pose and calibration parameters, and updates the 3D model according to the second frame. The projection unit projects the 3D model and the second frame onto the display unit according to the first pose for being displayed with a real image on the display unit.

Abstract: The gas turbine has a plurality of inlet guide vanes each having a blade having a leading edge, a trailing edge, a span extending along the leading edge, and pivot members at opposite ends of the leading edge, and being pivotally mounted across the radial-to-axial intake via the pivot members, the pivot axis extending axially across a radial portion of the radial-to-axial intake. The plurality of inlet guide vanes include a plurality of first inlet guide vanes, and a plurality of second inlet guide vanes, the second inlet guide vanes having a trailing edge recess differing from the corresponding portion of the first inlet guide vanes. During operation, when the inlet guide vanes are pivoted past a given angle toward the tangential orientation, a radial flow of gas is allowed through the trailing edge recesses to avoid or impede vortex whistle.