Patents by Inventor Chun Tse

Chun Tse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200161174
    Abstract: A method of making a semiconductor device includes depositing a first polysilicon layer over a substrate. The method further includes forming a barrier layer over the first polysilicon layer. The method further includes patterning the first polysilicon layer. The method further includes depositing a second polysilicon layer over the barrier layer, wherein the depositing of the second polysilicon layer comprises increasing a grain size of the first polysilicon layer, and causing at least one grain boundary in the first polysilicon layer to contact the barrier layer.
    Type: Application
    Filed: January 27, 2020
    Publication date: May 21, 2020
    Inventors: J. J. LEE, Chun-Tse TSAI, M. C. HANG
  • Patent number: 10649922
    Abstract: A system and method for efficiently scheduling requests. In various embodiments, a processor sends commands such as read requests and write requests to an arbiter. The arbiter reduces latencies between commands being sent to a communication fabric and corresponding data being sent to the fabric. When the arbiter selects a given request, the arbiter identifies a first subset of stored requests affected by the given request being selected. The arbiter adjusts one or more attributes of the first subset of requests based on the selection of the given request. In one example, the arbiter replaces a weight attribute with a value, such as a zero value, indicating the first subset of requests should not be selected. Therefore, during the next selection by the arbiter, only the requests in a second subset different from the first subset are candidates for selection.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: May 12, 2020
    Assignee: Apple Inc.
    Inventors: Shawn Munetoshi Fukami, Jaideep Dastidar, Yiu Chun Tse
  • Publication number: 20200057737
    Abstract: A system and method for efficiently arbitrating traffic on a bus. A computing system includes a fabric for routing traffic among one or more agents and one or more endpoints. The fabric includes multiple arbiters in an arbitration hierarchy. Arbiters store traffic in buffers with each buffer associated with a particular traffic type and a source of the traffic. Arbiters maintain a respective urgency counter for keeping track of a period of time traffic of a particular type is blocked by upstream arbiters. When the block is removed, the traffic of the particular type has priority for selection based on the urgency counter. When arbiters receive feedback from downstream arbiters or sources, the arbiters adjust selection priority accordingly. For example, changes in bandwidth requirement, low latency tolerance and active status cause adjustments in selection priority of stored requests.
    Type: Application
    Filed: August 20, 2018
    Publication date: February 20, 2020
    Inventors: Nachiappan Chidambaram Nachiappan, Jaideep Dastidar, Yiu Chun Tse, Ripudaman Singh, Shawn Munetoshi Fukami, Benjamin K. Dodge, Vinodh R. Cuppu
  • Publication number: 20200050379
    Abstract: A system and method for efficiently allocating data storage to agents. A computing system includes an interconnect with intermediate buffers for storing transactions and corresponding payload data during transport between sources and destinations. A data storage limit is set on an amount of data storage corresponding to outstanding transactions for each of the multiple sources based on the initial buffer assignments. A number of outstanding transactions for each of the multiple sources is limited based on a corresponding data storage limit. If the rate of allocation of a given buffer assigned to a first source exceeds a threshold, then a second source is selected with available space exceeding a threshold in an assigned buffer. If it is determined the second source is not assigned to a buffer with a rate of allocation exceeding a threshold, then buffer storage is reassigned from the second source to the first source.
    Type: Application
    Filed: August 9, 2018
    Publication date: February 13, 2020
    Inventors: Nachiappan Chidambaram Nachiappan, David L. Trawick, Yiu Chun Tse, Deniz Balkan, Hengsheng Geng, Shawn Munetoshi Fukami, Jaideep Dastidar, Benjamin K. Dodge, Vinodh R. Cuppu
  • Publication number: 20200042469
    Abstract: A system and method for efficiently scheduling requests. In various embodiments, a processor sends commands such as read requests and write requests to an arbiter. The arbiter reduces latencies between commands being sent to a communication fabric and corresponding data being sent to the fabric. When the arbiter selects a given request, the arbiter identifies a first subset of stored requests affected by the given request being selected. The arbiter adjusts one or more attributes of the first subset of requests based on the selection of the given request. In one example, the arbiter replaces a weight attribute with a value, such as a zero value, indicating the first subset of requests should not be selected. Therefore, during the next selection by the arbiter, only the requests in a second subset different from the first subset are candidates for selection.
    Type: Application
    Filed: August 6, 2018
    Publication date: February 6, 2020
    Inventors: Shawn Munetoshi Fukami, Jaideep Dastidar, Yiu Chun Tse
  • Patent number: 10553476
    Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a first polysilicon structure over the substrate. The first polysilicon structure has a first grain size. The semiconductor device further includes a first barrier layer over the first polysilicon structure. At least one grain boundary of the first polysilicon structure contacts the first barrier layer. The semiconductor device further includes a second polysilicon structure over the first barrier layer. The second polysilicon layer has a second grain size smaller than the first grain size.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: J. J. Lee, Chun-Tse Tsai, M. C. Hang
  • Publication number: 20190333286
    Abstract: A 3D model construction device includes a camera and a wearable display coupled to the camera. The camera obtains multiple first frames, a second frame and depth information. The wearable display includes a display unit, a processing unit, a storage unit and a projection unit. The storage unit stores a first module and a second module. When the first module is performed by the processing unit, the processing unit calculates a first pose of the wearable display. When the second module is performed by the processing unit, the processing unit calculates a 3D model according to the first frames, the depth information, the first pose and calibration parameters, and updates the 3D model according to the second frame. The projection unit projects the 3D model and the second frame onto the display unit according to the first pose for being displayed with a real image on the display unit.
    Type: Application
    Filed: April 25, 2019
    Publication date: October 31, 2019
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chun-Tse HSIAO, Chuan-Chi WANG, Chia-Chen CHEN
  • Patent number: 10423558
    Abstract: A system and method for efficiently routing data in a communication fabric. A computing system includes a fabric for routing data among one or more agents and a memory controller for system memory. The fabric includes multiple hierarchical clusters with a split topology where the data links are physically separated from the control links. A given cluster receives a write command and associated write data, and stores them in respective buffers. The given cluster marks the write command as a candidate to be issued to the memory controller when it is determined the write data will arrive ahead of the write command at the memory controller after being issued. The given cluster prevents the write command from becoming a candidate to be issued when it is determined the write data may not arrive ahead of the write command at the memory controller.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: September 24, 2019
    Assignee: Apple Inc.
    Inventors: Shawn Munetoshi Fukami, Yiu Chun Tse, David L. Trawick, Hengsheng Geng, Jaideep Dastidar, Vinodh R. Cuppu, Deniz Balkan
  • Patent number: 10255218
    Abstract: A system and method for efficiently bridging two communication protocols. In various embodiments, a computing system includes an interconnect for routing traffic among agents and endpoints. The agents use a first communication protocol and the endpoints use a second communication protocol that differs from the first protocol with regard to at least the ordering that is enforced between transactions. A bridge selects transactions of a first type and a second type used in the first protocol for processing based on the first protocol ordering while using acknowledgments used by the second protocol.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: April 9, 2019
    Assignee: Apple Inc.
    Inventors: Yiu Chun Tse, Deniz Balkan, Vinodh R. Cuppu, Shawn Munetoshi Fukami, Jaideep Dastidar, Hengsheng Geng
  • Publication number: 20180342417
    Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a first polysilicon structure over the substrate. The first polysilicon structure has a first grain size. The semiconductor device further includes a first barrier layer over the first polysilicon structure. At least one grain boundary of the first polysilicon structure contacts the first barrier layer. The semiconductor device further includes a second polysilicon structure over the first barrier layer. The second polysilicon layer has a second grain size smaller than the first grain size.
    Type: Application
    Filed: August 24, 2017
    Publication date: November 29, 2018
    Inventors: J. J. LEE, Chun-Tse TSAI, M. C. HANG
  • Publication number: 20180340434
    Abstract: The gas turbine has a plurality of inlet guide vanes each having a blade having a leading edge, a trailing edge, a span extending along the leading edge, and pivot members at opposite ends of the leading edge, and being pivotally mounted across the radial-to-axial intake via the pivot members, the pivot axis extending axially across a radial portion of the radial-to-axial intake. The plurality of inlet guide vanes include a plurality of first inlet guide vanes, and a plurality of second inlet guide vanes, the second inlet guide vanes having a trailing edge recess differing from the corresponding portion of the first inlet guide vanes. During operation, when the inlet guide vanes are pivoted past a given angle toward the tangential orientation, a radial flow of gas is allowed through the trailing edge recesses to avoid or impede vortex whistle.
    Type: Application
    Filed: May 25, 2017
    Publication date: November 29, 2018
    Inventors: Man-Chun TSE, Sid-Ali MESLIOUI
  • Patent number: 10056432
    Abstract: The present disclosure provides a self-rectifying RRAM cell structure including a first electrode layer formed of a nitride of a first metal element, a second electrode layer formed of a second metal element that is different from the first metal element, a first resistive switching layer and a second resistive switching layer. The first resistive switching layer is sandwiched between the first electrode layer and the second resistive switching layer, and the second resistive switching layer is sandwiched between the first resistive switching layer and the second electrode layer. The first resistive switching layer has a first bandgap that is lower than the second bandgap of the second resistive switching layer. Furthermore, a RRAM 3D crossbar array architecture is also provided.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: August 21, 2018
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Tuo-Hung Hou, Chung-Wei Hsu, Chun-Tse Chou, Wei-Li Lai
  • Patent number: 9978941
    Abstract: A self-rectifying resistive random access memory (RRAM) cell structure is provided. The self-rectifying RRAM cell structure includes a first electrode. An insulator-metal-transition (IMT) material layer is disposed on the first electrode. A barrier layer is disposed on the IMT material layer. A second electrode is disposed on the barrier layer. The IMT material layer is separated from the second electrode by the barrier layer.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: May 22, 2018
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Tuo-Hung Hou, Chung-Wei Hsu, Chun-Tse Chou
  • Patent number: 9850185
    Abstract: The present invention is concerned with a method of production of acetylene or ethylene. The method has the steps of providing supplies of hydrogen, water, carbon monoxide, carbon dioxide, and methane, respectively, providing a catalyst system having firstly a catalyst selected from group VIII transition metal oxides, and secondly a catalyst support, treating the methane supply with the catalyst system for producing a first reactant, providing a second reactant, and reacting the first reactant with the second reactant for producing an intermediate, wherein the intermediate is calcium carbide (CaC2).
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: December 26, 2017
    Assignee: Bestrong International Limited
    Inventors: Stefan Petters, Klaus Mauthner, Ka Chun Tse
  • Publication number: 20160152528
    Abstract: The present invention is concerned with a method of production of acetylene or ethylene. The method has the steps of providing supplies of hydrogen, water, carbon monoxide, carbon dioxide, and methane, respectively, providing a catalyst system having firstly a catalyst selected from group VIII transition metal oxides, and secondly a catalyst support, treating the methane supply with the catalyst system for producing a first reactant, providing a second reactant, and reacting the first reactant with the second reactant for producing an intermediate, wherein the intermediate is calcium carbide (CaC2).
    Type: Application
    Filed: November 23, 2015
    Publication date: June 2, 2016
    Applicant: Bestrong International Limited
    Inventors: Stefan PETTERS, Klaus MAUTHNER, Ka Chun TSE
  • Publication number: 20160093802
    Abstract: A self-rectifying resistive random access memory (RRAM) cell structure is provided. The self-rectifying RRAM cell structure includes a first electrode. An insulator-metal-transition (IMT) material layer is disposed on the first electrode. A barrier layer is disposed on the IMT material layer. A second electrode is disposed on the barrier layer. The IMT material layer is separated from the second electrode by the barrier layer.
    Type: Application
    Filed: September 15, 2015
    Publication date: March 31, 2016
    Inventors: TUO-HUNG HOU, CHUNG-WEI HSU, CHUN-TSE CHOU
  • Publication number: 20160064453
    Abstract: The present disclosure provides a self-rectifying RRAM cell structure including a first electrode layer formed of a nitride of a first metal element, a second electrode layer formed of a second metal element that is different from the first metal element, a first resistive switching layer and a second resistive switching layer. The first resistive switching layer is sandwiched between the first electrode layer and the second resistive switching layer, and the second resistive switching layer is sandwiched between the first resistive switching layer and the second electrode layer. The first resistive switching layer has a first bandgap that is lower than the second bandgap of the second resistive switching layer. Furthermore, a RRAM 3D crossbar array architecture is also provided.
    Type: Application
    Filed: June 5, 2015
    Publication date: March 3, 2016
    Inventors: Tuo-Hung HOU, Chung-Wei HSU, Chun-Tse CHOU, Wei-Li LAI
  • Patent number: 9208511
    Abstract: A method for providing a recommendation to a user, including retrieving, connection content associated with social network connections of the user; calculating, for each of the social network connections, an influence score for each of a plurality of locations; receiving a request location from a user device associated with the user; extracting a recommendation from relevant connection content, the relevant connection content being content associated with the request location and generated by at least one of the social network connections having the highest influence scores for the request location, the recommendation comprising a venue referenced within the relevant connection content; and sending the recommendation to the user device.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: December 8, 2015
    Assignee: Simple Rules, Inc.
    Inventors: Johnny Hsienchow Lee, Chun To Tse
  • Patent number: 9196750
    Abstract: Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a word line cell disposed over the substrate. The semiconductor device structure includes a substrate and a control gate formed over the substrate. The semiconductor device further includes an insulating layer formed on a sidewall of the control gate and a memory gate formed adjacent to the insulating layer. In addition, the insulating layer has a first height, and the memory gate has a second height shorter than the first height.
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: November 24, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Tse Tsai, Chia-Ping Lai
  • Publication number: 20150155394
    Abstract: Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a word line cell disposed over the substrate. The semiconductor device structure includes a substrate and a control gate formed over the substrate. The semiconductor device further includes an insulating layer formed on a sidewall of the control gate and a memory gate formed adjacent to the insulating layer. In addition, the insulating layer has a first height, and the memory gate has a second height shorter than the first height.
    Type: Application
    Filed: November 29, 2013
    Publication date: June 4, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Tse TSAI, Chia-Ping LAI