Patents by Inventor Chun W. Yeung
Chun W. Yeung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10957763Abstract: A semiconductor structure includes a substrate and a channel stack disposed over a portion of a top surface of the substrate, the channel stack including two or more nanosheet channels, inner spacers disposed above and below outer edges of the two or more nanosheet channels, work function metal disposed between the inner spacers above and below each of the two or more nanosheet channels, and a dielectric layer disposed between the work function metal and the inner spacers and two or more nanosheet channels. The semiconductor structure further includes source/drain regions disposed over the top surface of the substrate surrounding the channel stack and a gate region disposed over a top surface of the channel stack, the gate region including the work function metal and a gate metal disposed over the work function metal. The semiconductor structure further includes a capping layer and contacts.Type: GrantFiled: January 22, 2019Date of Patent: March 23, 2021Assignee: International Business Machines CorporationInventors: Chun W. Yeung, Chen Zhang
-
Patent number: 10930793Abstract: Provided is a nanosheet semiconductor device. In embodiments of the invention, the nanosheet semiconductor device includes a channel nanosheet formed over a substrate. The nanosheet semiconductor device includes a buffer layer formed between the substrate and the channel nanosheet. The buffer layer has a lower conductivity than the channel nanosheet.Type: GrantFiled: April 21, 2017Date of Patent: February 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robin H. Chao, Choonghyun Lee, Chun W. Yeung, Jingyun Zhang
-
Patent number: 10896816Abstract: A method for forming a nanosheet semiconductor device includes forming a nanosheet stack comprising channel nanosheets. The method includes depositing silicon on the nanosheet stack, the silicon completely filling a space between adjacent channel nanosheets. The method includes etching the silicon. The method includes exposing the nanosheet stack to a gas phase heat treatment.Type: GrantFiled: September 26, 2017Date of Patent: January 19, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Zhenxing Bi, Thamarai S. Devarajan, Nicolas J. Loubet, Binglin Miao, Muthumanickam Sankarapandian, Charan V. Surisetty, Chun W. Yeung, Jingyun Zhang
-
Patent number: 10804410Abstract: Provided is a nanosheet semiconductor device. In embodiments of the invention, the nanosheet semiconductor device includes a channel nanosheet formed over a substrate. The nanosheet semiconductor device includes a buffer layer formed between the substrate and the channel nanosheet. The buffer layer has a lower conductivity than the channel nanosheet.Type: GrantFiled: April 24, 2018Date of Patent: October 13, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robin H. Chao, Choonghyun Lee, Chun W. Yeung, Jingyun Zhang
-
Patent number: 10763327Abstract: A method of forming a semiconductor structure includes forming outer spacers surrounding a dummy gate, the dummy gate being disposed over a channel stack comprising two or more nanosheet channels and sacrificial layers formed above and below each of the two or more nanosheet channels. The method also includes forming an oxide surrounding the outer spacers, the oxide being disposed over source/drain regions surrounding the channel stack. The method further includes removing the dummy gate, removing the outer spacers, and performing a channel release to remove the sacrificial layers in the channel stack following removal of the outer spacers. The method further includes performing conformal deposition of a dielectric layer and a work function metal on exposed portions of the oxide, and filling a gate metal over the channel stack, the gate metal being surrounded by the work function metal.Type: GrantFiled: January 22, 2019Date of Patent: September 1, 2020Assignee: International Business Machines CorporationInventors: Chun W. Yeung, Chen Zhang
-
Patent number: 10734502Abstract: Semiconductor devices include semiconductor layers and a gate stack formed on and around the semiconductor layers. Spacers are formed between vertically adjacent semiconductor layers, each spacer having a first spacer layer and a second spacer layer. The first spacer layer is positioned between the gate stack and the second spacer layer. The second spacer layer of each spacer has a trapezoidal cross-section.Type: GrantFiled: November 6, 2019Date of Patent: August 4, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tenko Yamashita, Chun W. Yeung, Chen Zhang
-
Patent number: 10700195Abstract: Semiconductor devices and methods of forming the same include forming first charged spacers on sidewalls of a semiconductor fin. A gate stack on the fin is formed over the first charged spacers. Second charged spacers are formed on sidewalls of the fin above the gate stack. The fin is recessed to a height below a top level of the second charged spacers.Type: GrantFiled: February 14, 2019Date of Patent: June 30, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peng Xu, Chun W. Yeung, Chen Zhang
-
Publication number: 20200075744Abstract: Semiconductor devices include semiconductor layers and a gate stack formed on and around the semiconductor layers. Spacers are formed between vertically adjacent semiconductor layers, each spacer having a first spacer layer and a second spacer layer. The first spacer layer is positioned between the gate stack and the second spacer layer. The second spacer layer of each spacer has a trapezoidal cross-section.Type: ApplicationFiled: November 6, 2019Publication date: March 5, 2020Inventors: Tenko Yamashita, Chun W. Yeung, Chen Zhang
-
Patent number: 10573567Abstract: A method for forming a semiconductor device includes forming a fins on a substrate, forming a sacrificial gate stack over a channel region of the fins, a source/drain region with a first material on the fins, a first cap layer with a second material over the source/drain region, and a second cap layer with a third material on the first cap layer. A dielectric layer is deposited over the second cap layer. The sacrificial gate stack is removed to expose a channel region of the fins. A gate stack is formed over the channel region of the fins. A portion of the dielectric layer is removed to expose the second cap layer. The second cap layer and the first cap layer are removed to expose the source/drain region. A conductive material is deposited on the source/drain region.Type: GrantFiled: July 18, 2019Date of Patent: February 25, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Praneet Adusumilli, Zuoguang Liu, Shogo Mochizuki, Jie Yang, Chun W. Yeung
-
Patent number: 10541318Abstract: Semiconductor devices and methods of forming the same include forming a stack of layers of alternating materials, including first layers of sacrificial material and second layers of channel material. The first layers are recessed relative to the second layers with an etch that etches the second layers at a slower rate than the first layers to taper ends of the second layers. First spacers are formed in recesses formed by recessing the first layers. Second spacers are formed in recesses formed by recessing the first layers. The first spacers are etched to expose sidewalls of the second spacer. Source/drain extensions are formed in contact with exposed ends of the second layers.Type: GrantFiled: April 28, 2017Date of Patent: January 21, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tenko Yamashita, Chun W. Yeung, Chen Zhang
-
Publication number: 20190341318Abstract: A method for forming a semiconductor device includes forming a fins on a substrate, forming a sacrificial gate stack over a channel region of the fins, a source/drain region with a first material on the fins, a first cap layer with a second material over the source/drain region, and a second cap layer with a third material on the first cap layer. A dielectric layer is deposited over the second cap layer. The sacrificial gate stack is removed to expose a channel region of the fins. A gate stack is formed over the channel region of the fins. A portion of the dielectric layer is removed to expose the second cap layer. The second cap layer and the first cap layer are removed to expose the source/drain region. A conductive material is deposited on the source/drain region.Type: ApplicationFiled: July 18, 2019Publication date: November 7, 2019Inventors: Praneet Adusumilli, Zuoguang Liu, Shogo Mochizuki, Jie Yang, Chun W. Yeung
-
Patent number: 10453937Abstract: Methods of forming a semiconductor device include forming a layer of activating material on sidewalls of a stack of alternating layers of channel material and sacrificial material. The layer of activating material is annealed to cause the activating material to react with the sacrificial material and to form insulating spacers at ends of the layers of sacrificial material. The layer of activating material is etched away to expose ends of the layers of channel material. Source/drain regions are formed on the ends of the layers of channel material.Type: GrantFiled: December 8, 2017Date of Patent: October 22, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robinhsinku Chao, ChoongHyun Lee, Heng Wu, Chun W. Yeung, Jingyun Zhang
-
Patent number: 10431503Abstract: A method for forming a semiconductor device includes forming a fins on a substrate, forming a sacrificial gate stack over a channel region of the fins, a source/drain region with a first material on the fins, a first cap layer with a second material over the source/drain region, and a second cap layer with a third material on the first cap layer. A dielectric layer is deposited over the second cap layer. The sacrificial gate stack is removed to expose a channel region of the fins. A gate stack is formed over the channel region of the fins. A portion of the dielectric layer is removed to expose the second cap layer. The second cap layer and the first cap layer are removed to expose the source/drain region. A conductive material is deposited on the source/drain region.Type: GrantFiled: November 17, 2017Date of Patent: October 1, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Praneet Adusumilli, Zuoguang Liu, Shogo Mochizuki, Jie Yang, Chun W. Yeung
-
Patent number: 10411120Abstract: A method for manufacturing a semiconductor device includes forming a stacked configuration of first and second semiconductor layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region, performing an implantation of a semiconductor material on exposed portions of the stacked configuration in a source/drain region, wherein the implantation increases a concentration of the semiconductor material in the exposed portions of the stacked configuration, and selectively removing first semiconductor layers having an increased concentration of the semiconductor material from the source/drain region, wherein the removed first semiconductor layers correspond in position to the first semiconductor layers in the chaType: GrantFiled: July 20, 2017Date of Patent: September 10, 2019Assignee: International Business Machines CorporationInventors: Robin Hsin-Kuo Chao, Michael A. Guillorn, Chi-Chun Liu, Shogo Mochizuki, Chun W. Yeung
-
Patent number: 10396177Abstract: Methods of forming the same include forming a stack of layers of alternating materials, including first layers of sacrificial material and second layers of channel material. The first layers are recessed relative to the second layers with an etch that etches the second layers at a slower rate than the first layers to taper ends of the second layers. First spacers are formed in recesses formed by recessing the first layers. Second spacers are formed in recesses formed by recessing the first layers. The first spacers are etched to expose sidewalls of the second spacer. Source/drain extensions are formed in contact with exposed ends of the second layers.Type: GrantFiled: November 7, 2017Date of Patent: August 27, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tenko Yamashita, Chun W. Yeung, Chen Zhang
-
Patent number: 10361269Abstract: A method of forming a semiconductor structure includes forming a multi-layer structure. The multi-layer structure has a substrate and two or more nanosheet layers formed above the substrate. The method also includes forming a bottom isolation layer between the substrate and the two or more nanosheet layers. The method further includes performing a fin reveal in the multi-layer structure after formation of the bottom isolation layer to form a fin. The two or more nanosheet layers provide a channel stack for a nanosheet field-effect transistor.Type: GrantFiled: April 6, 2018Date of Patent: July 23, 2019Assignee: International Business Machines CorporationInventors: Chun W. Yeung, Chen Zhang
-
Patent number: 10332995Abstract: Semiconductor devices and methods of forming the same include forming semiconductor fins on a semiconductor substrate. A bottom source/drain region is formed in the semiconductor substrate. First charged dielectric spacers are formed on sidewalls of the semiconductor fins. A gate stack is formed over the bottom source/drain region. Second charged dielectric spacers are formed on sidewalls of the fin above the gate stack. The fins are recessed to a height below a top level of the second charged dielectric spacers. A top source/drain region is grown from the recessed fins.Type: GrantFiled: September 5, 2017Date of Patent: June 25, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peng Xu, Chun W. Yeung, Chen Zhang
-
Patent number: 10325815Abstract: A method of forming multiple vertical transport fin field effect transistors (VT FinFETs) having different channel lengths, including, forming a vertical fin on a first region of a substrate and a vertical fin on a second region of the substrate, forming a cover block on the vertical fin on the second region of the substrate, forming a first bottom source/drain on the first region of the substrate, wherein the first bottom source/drain covers a lower portion of the vertical fin on the first region, removing the cover block, and forming a second bottom source/drain in the second region of the substrate, wherein the second bottom source/drain is below the surface of the substrate, wherein the second bottom source/drain does not cover a lower portion of the vertical fin on the second region.Type: GrantFiled: April 26, 2018Date of Patent: June 18, 2019Assignee: International Business Machines CorporationInventors: Ruqiang Bao, Choonghyun Lee, Shogo Mochizuki, Chun W. Yeung
-
Patent number: 10326001Abstract: A semiconductor devices and methods of forming the same include forming a layer of activating material on sidewalls of a stack of alternating layers of channel material and sacrificial material. The layer of activating material is annealed to cause the activating material to react with the sacrificial material and to form insulating spacers at ends of the layers of sacrificial material. The layer of activating material is etched away to expose ends of the layers of channel material. Source/drain regions are formed on the ends of the layers of channel material.Type: GrantFiled: August 31, 2017Date of Patent: June 18, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robinhsinku Chao, ChoongHyun Lee, Heng Wu, Chun W. Yeung, Jingyun Zhang
-
Publication number: 20190181263Abstract: Semiconductor devices and methods of forming the same include forming first charged spacers on sidewalls of a semiconductor fin. A gate stack on the fin is formed over the first charged spacers. Second charged spacers are formed on sidewalls of the fin above the gate stack. The fin is recessed to a height below a top level of the second charged spacers.Type: ApplicationFiled: February 14, 2019Publication date: June 13, 2019Inventors: Peng Xu, Chun W. Yeung, Chen Zhang