Patents by Inventor Chun W. Yeung
Chun W. Yeung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180212038Abstract: A semiconductor devices and methods of forming the same include forming a layer of activating material on sidewalls of a stack of alternating layers of channel material and sacrificial material. The layer of activating material is annealed to cause the activating material to react with the sacrificial material and to form insulating spacers at ends of the layers of sacrificial material. The layer of activating material is etched away to expose ends of the layers of channel material. Source/drain regions are formed on the ends of the layers of channel material.Type: ApplicationFiled: August 31, 2017Publication date: July 26, 2018Inventors: Robinhsinku Chao, ChoongHyun Lee, Heng Wu, Chun W. Yeung, Jingyun Zhang
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Patent number: 10032867Abstract: A method of forming a semiconductor structure includes forming a multi-layer structure. The multi-layer structure has a substrate and two or more nanosheet layers formed above the substrate. The method also includes forming a bottom isolation layer between the substrate and the two or more nanosheet layers. The method further includes performing a fin reveal in the multi-layer structure after formation of the bottom isolation layer to form a fin. The two or more nanosheet layers provide a channel stack for a nanosheet field-effect transistor.Type: GrantFiled: March 7, 2017Date of Patent: July 24, 2018Assignee: International Business Machines CorporationInventors: Chun W. Yeung, Chen Zhang
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Publication number: 20180197990Abstract: Semiconductor devices and methods of forming the same include forming a bottom source/drain region in a semiconductor substrate under a semiconductor fin. First charged spacers are formed on sidewalls of the semiconductor fin. A gate stack is formed on the fin, over the first charged spacers. Second charged spacers are formed on sidewalls of the fin above the gate stack. The fin is recessed to a height below a top level of the second charged spacers. A top source/drain region is grown from the recessed fin.Type: ApplicationFiled: December 21, 2017Publication date: July 12, 2018Inventors: Peng Xu, Chun W. Yeung, Chen Zhang
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Publication number: 20180197989Abstract: Semiconductor devices and methods of forming the same include forming semiconductor fins on a semiconductor substrate. A bottom source/drain region is formed in the semiconductor substrate. First charged dielectric spacers are formed on sidewalls of the semiconductor fins. A gate stack is formed over the bottom source/drain region. Second charged dielectric spacers are formed on sidewalls of the fin above the gate stack. The fins are recessed to a height below a top level of the second charged dielectric spacers. A top source/drain region is grown from the recessed fins.Type: ApplicationFiled: September 5, 2017Publication date: July 12, 2018Inventors: Peng Xu, Chun W. Yeung, Chen Zhang
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Patent number: 10020400Abstract: Semiconductor devices with airgap spacers and methods of forming the same include forming a lower spacer that defines a gate region. A sacrificial upper spacer is formed directly above the lower spacer. A gate stack is formed in the gate region. The sacrificial upper spacer is etched away to form an upper spacer opening. An airgap spacer is formed in the upper spacer opening. The airgap spacer includes a dielectric material that encapsulates an internal void.Type: GrantFiled: August 3, 2017Date of Patent: July 10, 2018Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Zuoguang Liu, Chun W. Yeung
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Patent number: 10008417Abstract: A method of forming multiple vertical transport fin field effect transistors (VT FinFETs) having different channel lengths, including, forming a vertical fin on a first region of a substrate and a vertical fin on a second region of the substrate, forming a cover block on the vertical fin on the second region of the substrate, forming a first bottom source/drain on the first region of the substrate, wherein the first bottom source/drain covers a lower portion of the vertical fin on the first region, removing the cover block, and forming a second bottom source/drain in the second region of the substrate, wherein the second bottom source/drain is below the surface of the substrate, wherein the second bottom source/drain does not cover a lower portion of the vertical fin on the second region.Type: GrantFiled: June 12, 2017Date of Patent: June 26, 2018Assignee: International Business Machines CorporationInventors: Ruqiang Bao, Choonghyun Lee, Shogo Mochizuki, Chun W. Yeung
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Patent number: 9947767Abstract: A semiconductor devices and methods of forming the same include forming a layer of activating material on sidewalls of a stack of alternating layers of channel material and sacrificial material. The layer of activating material is annealed to cause the activating material to react with the sacrificial material and to form insulating spacers at ends of the layers of sacrificial material. The layer of activating material is etched away to expose ends of the layers of channel material. Source/drain regions are formed on the ends of the layers of channel material.Type: GrantFiled: January 26, 2017Date of Patent: April 17, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robinhsinku Chao, ChoongHyun Lee, Heng Wu, Chun W. Yeung, Jingyun Zhang
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Patent number: 9935195Abstract: Semiconductor devices and methods of forming the same include forming semiconductor fins on a semiconductor substrate. A bottom source/drain region is formed in the semiconductor substrate. First charged dielectric spacers are formed on sidewalls of the semiconductor fins. A gate stack is formed over the bottom source/drain region. Second charged dielectric spacers are formed on sidewalls of the fin above the gate stack. The fins are recessed to a height below a top level of the second charged dielectric spacers. A top source/drain region is grown from the recessed fins.Type: GrantFiled: January 12, 2017Date of Patent: April 3, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peng Xu, Chun W. Yeung, Chen Zhang
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Publication number: 20180082909Abstract: A method for forming a semiconductor device includes forming a fins on a substrate, forming a sacrificial gate stack over a channel region of the fins, a source/drain region with a first material on the fins, a first cap layer with a second material over the source/drain region, and a second cap layer with a third material on the first cap layer. A dielectric layer is deposited over the second cap layer. The sacrificial gate stack is removed to expose a channel region of the fins. A gate stack is formed over the channel region of the fins. A portion of the dielectric layer is removed to expose the second cap layer. The second cap layer and the first cap layer are removed to expose the source/drain region. A conductive material is deposited on the source/drain region.Type: ApplicationFiled: November 17, 2017Publication date: March 22, 2018Inventors: Praneet Adusumilli, Zuoguang Liu, Shogo Mochizuki, Jie Yang, Chun W. Yeung
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Publication number: 20180053830Abstract: A semiconductor device includes a semiconductor substrate including a channel region and a source/drain region, and an electrically conductive gate on an upper surface of the channel region. An electrically conductive source/drain contact is on an upper surface of the source/drain region. The semiconductor device further includes enhanced low-k spacer on an upper surface of the substrate and interposed between the electrically conductive gate and the electrically conductive source/drain contact. The enhanced low-k spacer includes a stacked arrangement of a dielectric material and a ferroelectric material.Type: ApplicationFiled: August 19, 2016Publication date: February 22, 2018Inventors: Kangguo Cheng, Zuoguang Liu, Chun W. Yeung
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Publication number: 20180047835Abstract: A method for manufacturing a semiconductor device includes forming a stacked configuration of first and second semiconductor layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region, performing an implantation of a semiconductor material on exposed portions of the stacked configuration in a source/drain region, wherein the implantation increases a concentration of the semiconductor material in the exposed portions of the stacked configuration, and selectively removing first semiconductor layers having an increased concentration of the semiconductor material from the source/drain region, wherein the removed first semiconductor layers correspond in position to the first semiconductor layers in the chaType: ApplicationFiled: July 20, 2017Publication date: February 15, 2018Inventors: Robin Hsin-Kuo Chao, Michael A. Guillorn, Chi-Chun Liu, Shogo Mochizuki, Chun W. Yeung
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Publication number: 20180047834Abstract: A method for manufacturing a semiconductor device includes forming a stacked configuration of first and second semiconductor layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region, performing an implantation of a semiconductor material on exposed portions of the stacked configuration in a source/drain region, wherein the implantation increases a concentration of the semiconductor material in the exposed portions of the stacked configuration, and selectively removing first semiconductor layers having an increased concentration of the semiconductor material from the source/drain region, wherein the removed first semiconductor layers correspond in position to the first semiconductor layers in the chaType: ApplicationFiled: July 20, 2017Publication date: February 15, 2018Inventors: Robin Hsin-Kuo Chao, Michael A. Guillorn, Chi-Chun Liu, Shogo Mochizuki, Chun W. Yeung
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Publication number: 20170358673Abstract: Semiconductor devices with airgap spacers and methods of forming the same include forming a lower spacer that defines a gate region. A sacrificial upper spacer is formed directly above the lower spacer. A gate stack is formed in the gate region. The sacrificial upper spacer is etched away to form an upper spacer opening. An airgap spacer is formed in the upper spacer opening. The airgap spacer includes a dielectric material that encapsulates an internal void.Type: ApplicationFiled: August 3, 2017Publication date: December 14, 2017Inventors: Kangguo Cheng, Zuoguang Liu, Chun W. Yeung
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Patent number: 9842914Abstract: A method of forming a semiconductor device and resulting structures having stacked nanosheets with a wrap-around inner spacer by forming a nanosheet stack disposed above a substrate; forming a top sacrificial layer on a top surface of the nanosheet stack; forming a sidewall sacrificial layer on two opposite sidewalls of the nanosheet stack, such that a first and a second end of a first vertically-stacked nanosheet are exposed; removing the sidewall sacrificial layer, a portion of a first and a second end of a first sacrificial layer, and a portion of a first and a second end of a top sacrificial layer to expose portions of the first vertically-stacked nanosheet; and forming an inner spacer region on the first vertically-stacked nanosheet to replace the removed sidewall sacrificial layer, the removed portions of the first sacrificial layer, and the removed portions of the top sacrificial layer.Type: GrantFiled: August 19, 2016Date of Patent: December 12, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chun W. Yeung, Chen Zhang
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Patent number: 9831324Abstract: A method for manufacturing a semiconductor device includes forming a stacked configuration of first and second semiconductor layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region, performing an implantation of a semiconductor material on exposed portions of the stacked configuration in a source/drain region, wherein the implantation increases a concentration of the semiconductor material in the exposed portions of the stacked configuration, and selectively removing first semiconductor layers having an increased concentration of the semiconductor material from the source/drain region, wherein the removed first semiconductor layers correspond in position to the first semiconductor layers in the chaType: GrantFiled: August 12, 2016Date of Patent: November 28, 2017Assignee: International Business Machines CorporationInventors: Robin Hsin-Kuo Chao, Michael A. Guillorn, Chi-Chun Liu, Shogo Mochizuki, Chun W. Yeung
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Patent number: 9805989Abstract: A method for forming a semiconductor device includes forming a fins on a substrate, forming a sacrificial gate stack over a channel region of the fins, a source/drain region with a first material on the fins, a first cap layer with a second material over the source/drain region, and a second cap layer with a third material on the first cap layer. A dielectric layer is deposited over the second cap layer. The sacrificial gate stack is removed to expose a channel region of the fins. A gate stack is formed over the channel region of the fins. A portion of the dielectric layer is removed to expose the second cap layer. The second cap layer and the first cap layer are removed to expose the source/drain region. A conductive material is deposited on the source/drain region.Type: GrantFiled: September 22, 2016Date of Patent: October 31, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Praneet Adusumilli, Zuoguang Liu, Shogo Mochizuki, Jie Yang, Chun W. Yeung
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Publication number: 20170243968Abstract: Semiconductor devices with airgap spacers and methods of forming the same include forming a lower spacer that defines a gate region. A sacrificial upper spacer is formed directly above the lower spacer. A gate stack is formed in the gate region. The sacrificial upper spacer is etched away to form an upper spacer opening. An airgap spacer is formed in the upper spacer opening. The airgap spacer includes a dielectric material that encapsulates an internal void.Type: ApplicationFiled: November 3, 2016Publication date: August 24, 2017Inventors: Kangguo Cheng, Zuoguang Liu, Chun W. Yeung
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Patent number: 9673293Abstract: Semiconductor devices with airgap spacers and methods of forming the same include forming a lower spacer that defines a gate region. A sacrificial upper spacer is formed directly above the lower spacer. A gate stack is formed in the gate region. The sacrificial upper spacer is etched away to form an upper spacer opening. An airgap spacer is formed in the upper spacer opening. The airgap spacer includes a dielectric material that encapsulates an internal void.Type: GrantFiled: February 18, 2016Date of Patent: June 6, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Zuoguang Liu, Chun W. Yeung
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Patent number: 7983646Abstract: Various embodiments to reduce radio frequency noise are described. An apparatus may comprise a mobile computing device having a radio frequency noise reduction module to disable a radio frequency noise source in response to a receive active signal from a radio receiver. Other embodiments are described and claimed.Type: GrantFiled: December 7, 2006Date of Patent: July 19, 2011Assignee: Hewlett-Packard Development Company, L.P.Inventors: Olivier Boireau, Gary Embler, Avi Kopelman, William Noellert, Karl Townsend, Chun W. Yeung
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Publication number: 20080139155Abstract: Various embodiments to reduce radio frequency noise are described. An apparatus may comprise a mobile computing device having a radio frequency noise reduction module to disable a radio frequency noise source in response to a receive active signal from a radio receiver. Other embodiments are described and claimed.Type: ApplicationFiled: December 7, 2006Publication date: June 12, 2008Inventors: OLIVIER BOIREAU, GARY EMBLER, AVI KOPELMAN, WILLIAM NOELLERT, KARL TOWNSEND, CHUN W. YEUNG