Patents by Inventor Chun Wang

Chun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250239499
    Abstract: An ultra-thin packaged component and its manufacturing method are provided. The packaged component includes a die, at least one conductive component, an encapsulant layer, and multiple conductive contacts. The encapsulant layer surrounds and covers the die and the conductive component, with multiple conductive contacts placed on the surface of the encapsulant layer that electrically connect the die and the conductive component. During the manufacturing of the packaged component, the die and the conductive component are first encapsulated with the encapsulant layer and then simultaneously thinned through grinding. Such process protects the die with the encapsulant layer to prevent cracking and reduces the thickness of the base layer of the die closer to that of its epitaxy layer, achieving the objective of thinness.
    Type: Application
    Filed: July 5, 2024
    Publication date: July 24, 2025
    Inventors: CHUNG-HSIUNG HO, CHIEN-CHUN WANG, CHI-HSUEH LI, WEI-MING HUNG, JENG-SIAN WU
  • Patent number: 12367628
    Abstract: Apparatuses, systems, and techniques are presented to generate digital content. In at least one embodiment, one or more neural networks are used to generate video information based at least in part upon voice information and a combination of image features and facial landmarks corresponding to one or more images of a person.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: July 22, 2025
    Assignee: NVIDIA Corporation
    Inventors: Siddharth Gururani, Arun Mallya, Ting-Chun Wang, Jose Rafael Valle da Costa, Ming-Yu Liu
  • Patent number: 12362873
    Abstract: Embodiments of the present invention provide an improved switching mechanism for multi-link devices that can perform frame exchanges using multiple spatial streams and automatically switch back to a listening mode on enabled links deterministically for improved throughput and reduced latency. Embodiments of the present invention are suitable for multi-link operations performed using a multi-radio device or a single-radio device.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: July 15, 2025
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Kai Ying Lu, James Chih-Shi Yee, Yongho Seok, Chao-Chun Wang
  • Patent number: 12354959
    Abstract: Semiconductor structures and method of forming the same are provided. A semiconductor structure according to the present disclosure includes a contact feature in a dielectric layer, a passivation structure over the dielectric layer, a conductive feature over the passivation structure, a seed layer disposed between the conductive feature and the passivation structure, a protecting layer disposed along sidewalls of the conductive feature, and a passivation layer over the conductive feature and the protecting layer.
    Type: Grant
    Filed: June 5, 2023
    Date of Patent: July 8, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Chun Wang, Tzy-Kuang Lee, Chih-Hsien Lin, Ching-Hung Kao, Yen-Yu Chen
  • Publication number: 20250218793
    Abstract: Some implementations herein include a semiconductor die and methods of formation. The semiconductor die includes an array of interconnect pad structures, including interconnect pad structures having surfaces located within an overlay region of an active device area of the semiconductor die. As part of manufacturing the semiconductor die, temporary conductive structures are formed across the overlay region to support wafer acceptance testing and/or circuit probe testing process. Forming the temporary conductive structures includes using an anti-reflective coating layer having a composition that enables the temporary conductive structures to be formed using a single etch cycle.
    Type: Application
    Filed: December 29, 2023
    Publication date: July 3, 2025
    Inventors: I-Chun WANG, Ching-Sheng CHU, Chern-Yow HSU, Yi-Fong LAI, We-Dung TSAI, Kong-Beng THEI, Jung-Hui KAO, Jing-Jung HUANG
  • Publication number: 20250212372
    Abstract: A power supply unit with improved space utilization and heat dissipation, including a heat-dissipation case, a circuit board and a plurality of electronic components; the circuit board is disposed in the heat-dissipation case, and has a first deployment surface and a second deployment surface in opposite positions; the plurality of electronic components include at least one power component and other electronic components, wherein the other electronic components are disposed on the first deployment surface of the circuit board, and the at least one power component is disposed on the second deployment surface of the circuit board and connects to an inner surface of the heat-dissipation case.
    Type: Application
    Filed: January 22, 2024
    Publication date: June 26, 2025
    Inventors: CHIEN-CHUN WANG, CHE FANG, CHI-HSUEH LI, CHUNG-HSIUNG HO
  • Publication number: 20250208453
    Abstract: The disclosure provides an anti-peep module and a display device. The anti-peep module includes an anisotropic diffusion film, an electrically controlled phase retarder, and a first polarizer. The anisotropic diffusion film includes a substrate, multiple first optical microstructures, and a first liquid crystal layer. The first optical microstructures are arranged along a first direction and extend in a second direction. The first liquid crystal layer directly covers the first optical microstructures. An optical axis of the first liquid crystal layer is parallel to the second direction. A difference value of a refractive index of the first optical microstructures and one of a first refractive index and a second refractive index of the first liquid crystal layer along the first direction and the second direction respectively is greater than or equal to 0.05. A first absorption axis of the first polarizer is parallel to or perpendicular to the second direction.
    Type: Application
    Filed: December 17, 2024
    Publication date: June 26, 2025
    Applicant: Coretronic Corporation
    Inventors: Ping-Yen Chen, Chung-Yang Fang, Wen-Chun Wang, Jen-Wei Yu
  • Patent number: 12342633
    Abstract: The present invention provides a photovoltaic panel packaging structure and method for the same. The packaging structure comprises a frame and a solar photovoltaic panel. The solar photovoltaic panel includes a first frame surface and a second frame surface with a receiving space and grooves formed therein. The a solar photovoltaic panel is installed in the receiving space and stacked on top of a first stop portion. The solar photovoltaic panel includes a first encapsulating layer, a second encapsulating layer. The first encapsulating layer includes a plurality of engaging strips extending along the edges of the solar photovoltaic panel, the engaging strips are respectively embedded in the corresponding grooves to hold the solar photovoltaic panel in place in the frame. Meanwhile, a third encapsulating layer extends to connect to the second frame surface. As a result, weight and thickness can be reduced while reducing multiple packaging passes and simplifying the assembly process.
    Type: Grant
    Filed: July 17, 2023
    Date of Patent: June 24, 2025
    Assignees: A SUN DRAGON ENERGY CO., LTD., PU TIEN INVESTMENT CO., LTD.
    Inventors: Yao-Chung Hsiao, Hui-Yun Wu, Hung-Chun Wang, Yu-Sheng Kuo
  • Publication number: 20250199548
    Abstract: Disclosed in the present invention is a shuttle vehicle traveling and positioning control method based on encoder self-correction. Provided is a self-correction solution based on track positioning identifiers and external encoders. When a shuttle vehicle travels through each identifier, information is fed back and a servo target position is updated instantaneously, so as to eliminate, at any time, a cumulative error caused by skidding; and the shuttle vehicle realizes a full-closed-loop traveling and positioning control process under the guidance of position information which is corrected at any time. The shuttle vehicle traveling and positioning control method based on encoder self-correction comprises the following implementation stages: 1) performing customization and initialization; 2) performing self-learning; 3) performing self-correction; 4) updating a target position; and 5) handling a position offset.
    Type: Application
    Filed: March 4, 2025
    Publication date: June 19, 2025
    Inventors: Yuan Sun, Jiahao Jiang, Guangyong Li, Chun Wang, Maojin Jiao
  • Patent number: 12333638
    Abstract: Apparatuses, systems, and techniques are presented to reconstruct one or more images. In at least one embodiment, one or more neural networks are used to generate one or more images of one or more objects based, at least in part, on input indicating motion of the one or more objects.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: June 17, 2025
    Assignee: NVIDIA Corporaton
    Inventors: Ting-Chun Wang, Tim Brooks, Ming-Yu Liu, Tero Karras, Jaakko Lehtinen
  • Patent number: 12336217
    Abstract: Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile, by the thermal hydrogen treatment.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: June 17, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Ta Wu, Cheng-Wei Chen, Shiu-Ko Jangjian, Ting-Chun Wang
  • Publication number: 20250194023
    Abstract: An information handling system may include a circuit board, a shock detector mounted on the circuit board, and a detection circuit electrically coupled to the shock detector. The shock detector may be configured to complete an electrical circuit in a first state in an absence of a threshold mechanical force applied to the information handling system and to have an impedance discontinuity in a second state in a presence of the threshold mechanical force. The detection circuit may be configured to detect whether the impedance discontinuity exists.
    Type: Application
    Filed: December 6, 2023
    Publication date: June 12, 2025
    Applicant: Dell Products L.P.
    Inventors: Craig L. CHAIKEN, Hong-Ling CHEN, Hou-Chun WANG
  • Publication number: 20250192810
    Abstract: This application provides a signal processing system, a remote radio unit, and an antenna unit. The signal processing system includes N baseband transmit units, a first power balancing module, a second power balancing module, N baseband receive units, and an antenna unit. The antenna unit includes N antenna ports and a third power balancing module. The first power balancing module and the second power balancing module may be configured to perform power balancing on a plurality of digital signals in an uplink direction and a downlink direction respectively, and the third power balancing module may be configured to perform power balancing on radio frequency signals in the uplink direction and the downlink direction. Therefore, based on this structure, power sharing between different sectors in the downlink direction can be implemented, and an existing RRU structure is adapted.
    Type: Application
    Filed: February 24, 2025
    Publication date: June 12, 2025
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Chun WANG, Wunan YANG, Chunlin XUE, Bing YANG, Xuan YI
  • Publication number: 20250185374
    Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.
    Type: Application
    Filed: February 11, 2025
    Publication date: June 5, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Lun CHIEN, Po-Chun WANG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Li-Chun TIEN
  • Publication number: 20250173854
    Abstract: Disclosed is a manufacturing process optimization method, and more particularly relates to a voice coil winding real-time quality control method, system, and a corresponding apparatus. In the method as disclosed, the influence model is built via data analysis to calibrate relevancy between product quality and production line-related performance input parameter, which allows for directing a commissioning technician to perform remote, targeted parameter adjustment, without constant trial and error on the production line or shutting down the production line for adjustment like in conventional technologies; the method disclosed herein enhances production line throughput stability and can effectively improve the yield rate and work efficiency of the voice coil production line.
    Type: Application
    Filed: August 6, 2024
    Publication date: May 29, 2025
    Inventors: Zhichen Chen, Liang Chen, Xuelei Cai, Qicong Zhu, Yuemei Gu, Qunfeng Jiang, Chuang Du, Chun Wang, Yuan Gu
  • Publication number: 20250176198
    Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.
    Type: Application
    Filed: January 30, 2025
    Publication date: May 29, 2025
    Inventors: Hsuan-Han Tseng, Chun-Yuan Chen, Lu-Sheng Chou, Hsiao-Hui Tseng, Ching-Chun Wang
  • Patent number: 12315843
    Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, the 3D IC comprises a first IC die comprising a first substrate, a first interconnect structure disposed over the first substrate, and a first through substrate via (TSV) disposed through the first substrate. The 3D IC further comprises a second IC die comprising a second substrate, a second interconnect structure disposed over the second substrate, and a second TSV disposed through the second substrate. The 3D IC further comprises a bonding structure arranged between back sides of the first IC die and the second IC die opposite to corresponding interconnect structures and bonding the first IC die and the second IC die. The bonding structure comprises conductive features disposed between and electrically connecting the first TSV and the second TSV.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: May 27, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Ming Wu, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao, Yung-Lung Lin, Shih-Han Huang, I-Nan Chen
  • Patent number: 12314954
    Abstract: The present disclosure provides a multi-factor authentication system for self-service energy replenishing and method thereof. A user may acquire a multi-factor authentication service by an application for experiencing a convenient and safe self-service energy replenishing service. During the registration stage, registration stage upon the user logging into the application of the multi-factor authentication system, the user may complete tasks of identity authentication, account setup (such as obtain a membership of the energy replenishing station), and obtain permission of use for the account, thereby enabling the user to access services provided by the multi-factor authentication service platform.
    Type: Grant
    Filed: July 5, 2024
    Date of Patent: May 27, 2025
    Inventor: Chih-Chun Wang
  • Publication number: 20250166237
    Abstract: Apparatuses, processors, computing systems, devices, non-transitory computer medium, and/or methods for using neural networks for generating multiple related images. In at least one embodiment, a processor includes circuitry to use one or more neural networks to generate several images, where each image includes a same object (e.g., same subject) and different backgrounds. For example, a processor including one or more circuits to use one or more neural networks to generate one or more objects (e.g., an animal, a vehicle, a person) within two or more different images (e.g., different backgrounds such as weather, season, environment) based, at least in part, on one or more indications (e.g., text prompts) by one or more users indicating content of at least one of the two or more different images (e.g., objects and/or backgrounds for each image in text such as adjectives and nouns) other than the one or more objects.
    Type: Application
    Filed: November 22, 2023
    Publication date: May 22, 2025
    Inventors: Yu Zeng, Yogesh Balaji, Ting-Chun Wang, Xun Huang, Ming-Yu Liu
  • Patent number: D1079659
    Type: Grant
    Filed: February 1, 2024
    Date of Patent: June 17, 2025
    Assignee: Guangzhou Ting Shen Electric Co., Ltd
    Inventor: Chia-Chun Wang