Abstract: A method of forming a semiconductor structure is provided, and includes trimming a first substrate to form a recess on a sidewall of the first substrate. A conductive structure is formed in the first substrate. The method includes bonding the first substrate to a carrier. The method includes thinning down the first substrate. The method also includes forming a dielectric material in the recess and over a top surface of the thinned first substrate. The method further includes performing a planarization process to remove the dielectric material and expose the conductive structure over the top surface. In addition, the method includes removing the carrier from the first substrate.

Abstract: Methods and systems for operating a voltage regulator are described. A integrated circuit can be configured to adjust at least one of a deadtime parameter and a drive strength parameter of a power stage based on at least one of an input voltage being provided to a power stage, a switch node voltage of the power stage, and an output current of the power stage. A controller of the power stage can be further configured to adjust a deadtime of the power stage based on adjustment of the deadtime parameter. The controller can be further configured to adjust a drive strength of the first driver and the second driver based on adjustment of the drive strength parameter.

Abstract: A wearable electronic device including: a first portion and a second portion. The first portion includes a first conductive area on a first inner surface of the first portion and a third conductive area on a first outer surface of the first portion. The second portion includes one or more second conductive areas on a second outer surface of the second portion and a fourth conductive area on a second inner surface of the second portion, wherein the first portion is connected to the second portion. A circuit unit is disposed in a second space of the second portion, wherein the circuit unit is configured to enable an input/output unit of the circuit unit in response to the first conductive area and the second conductive areas are triggered.

Abstract: The present disclosure provides a speaker diaphragm and a speaker. The diaphragm includes a thermoplastic polyester elastomer film layer, a thermoplastic polyester elastomer being a copolymer composed of a hard segment A of polyester and a soft segment B of polyether or aliphatic polyester, wherein the thermoplastic polyester elastomer film layer has Young's modulus of 1-1000 MPa, with an elastic recovery rate after 10% strain being greater than or equal to 80%. The speaker diaphragm has a good stiffness, a good damping performance and a good resilience.

Abstract: A method of performing air pollution estimation is provided. The method is to be implemented using a processor of a computer device and includes: generating a spectral image based on an original color image of an environment under test using a spectral transformation matrix; supplying the spectral image as an input into an estimating model for air pollution estimation; and obtaining an estimation result from the estimating model indicating a degree of air pollution of the environment under test.

Abstract: Improved conductive contacts, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a first interlayer dielectric (ILD) layer over a transistor structure; a first contact extending through the first ILD layer, the first contact being electrically coupled with a first source/drain region of the transistor structure, a top surface of the first contact being convex, and the top surface of the first contact being disposed below a top surface of the first ILD layer; a second ILD layer over the first ILD layer and the first contact; and a second contact extending through the second ILD layer, the second contact being electrically coupled with the first contact.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes device fins formed on a substrate; fill fins formed on the substrate and disposed among the device fins; and gate stacks formed on the device fins and the fill fins. The fill fins include a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer. The first and second dielectric material layers are different from each other in composition.

Abstract: A conductive structure is applied to an e-paper device, which includes a driving substrate and an e-paper film. The e-paper film is disposed on the driving substrate, and includes a transparent substrate, a common electrode layer, and a display medium layer disposed between the common electrode layer and the driving substrate. The common electrode layer is disposed on one side of the transparent substrate facing the driving substrate. The display medium layer includes a through hole. The conductive structure is disposed in the through hole and includes a conductive member and at least one spacer. The conductive member is electrically connected to the driving substrate and the common electrode layer. The spacer is disposed in/on the conductive member, and contacts with the driving substrate and the common electrode layer. An e-paper device with the conductive structure is also disclosed.

Abstract: The present disclosure provides a ball tracking system and method. The ball tracking system includes camera device and processing device. The camera device is configured to generate a plurality of video frame data, wherein the video frame data includes image of ball. The processing device is electrically coupled to the camera device and is configured to: recognize the image of the ball from the plurality of video frame data to obtain 2D estimation coordinate of the ball at first frame time and utilize 2D to 3D matrix to convert the 2D estimation coordinate into first 3D estimation coordinate; utilize model to calculate second 3D estimation coordinate of the ball at the first frame time; and calibrate according to the first 3D estimation coordinate and the second 3D estimation coordinate to generate 3D calibration coordinate of the ball at the first frame time.

Abstract: A light-emitting device includes a substrate, a semiconductor epitaxial structure, and an etch stop layer. The substrate has a first surface and a second surface opposite to the first surface. The semiconductor epitaxial structure has a side surface that has a roughened structure formed with protrusions, and includes a first type semiconductor layer, an active layer, and a second type semiconductor layer disposed on the first surface of the substrate in such order. The etch stop layer is disposed on a surface of the semiconductor epitaxial structure away from the substrate for preventing an etching solution from etching the semiconductor epitaxial structure. A light-emitting package and a light-emitting apparatus are also provided. A method for manufacturing a light-emitting device is also provided.

Abstract: 2-hydroxy-5-[2-(4-(trifluoromethylphenyl)ethylamino)]benzoic acid crystal forms and a preparation method therefor are proposed. Crystal form I is a monoclinic crystal system, which has a Pc space group and can be obtained by slow cooling, evaporating the solvent at a constant temperature, evaporating the solvent at an increased temperature, or adding an anti-solvent. Crystal form II is a triclinic crystal system, which has a P1 space group and can be obtained by rapid cooling or freeze-drying. According to the method, the process is simple, costs are low, and the yield exceeds 90%; and the crystal forms of the crystal forms I and II have high purity, the crystal shapes thereof are intact, and have excellent fluidity, facilitating preparation, particularly the preparation of a pharmaceutical preparation for preventing and/or treating degenerative diseases of the central nervous system. Furthermore, the two crystal forms have a better apparent solubility than that of raw materials.

Abstract: A chip package includes a substrate, a semiconductor chip, and a thermal conductive structure. The chip package includes a first and a second support structures below the thermal conductive structure. The first and the second support structures connect the substrate and corners of the thermal conductive structure. The thermal conductive structure has a side edge connecting the first and the second support structures. The first and the second support structures and the side edge together define of an opening exposing a space surrounding the semiconductor chip. The first and the second support structures are disposed along a side of the substrate. The first support structure is laterally separated from the side of the substrate by a first lateral distance. The side edge of the thermal conductive structure is laterally separated from the side of the substrate by a second lateral distance different than the first lateral distance.

Abstract: The present invention provides an electrostatic charge detecting packaging device comprising a carrier, multiple dies, and multiple electrostatic-charge-sensitive components; the carrier has a surface; the dies are mounted on the surface of the carrier; and the electrostatic-charge-sensitive components are mounted on the surface of the carrier; since an electrostatic voltage tolerance of each of the electrostatic-charge-sensitive components is lower than an electrostatic voltage tolerance of each of the dies, accumulated electrostatic charges are more likely to discharge towards the electrostatic-charge-sensitive components than towards the dies, and as such, by electrically testing whether the electrostatic-charge-sensitive components are functioning normally when packaging the dies, the present invention allows personnel to debug for knowing which packaging steps exactly cause more serious problems that lead to damaging electrostatic discharges in the dies.

Abstract: In a method of coating a photo resist over a wafer, dispensing the photo resist from a nozzle over the wafer is started while rotating the wafer, and dispensing the photo resist is stopped while rotating the wafer. After starting and before stopping the dispensing the photo resist, a wafer rotation speed is changed at least 4 times. During dispensing, an arm holding the nozzle may move horizontally. A tip end of the nozzle may be located at a height of 2.5 mm to 3.5 mm from the wafer.

Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.

Abstract: An interconnect structure comprises a first dielectric layer, a first metal layer, a second dielectric layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer. The first metal layer comprises a first portion and a second portion spaced apart from the first portion. The second dielectric layer is over the first metal layer. The metal via has an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first metal layer, and a lower portion in the first dielectric layer. The second metal layer is over the metal via. From a top view the second metal layer comprises a metal line having longitudinal sides respectively set back from opposite sides of the first portion of the first metal layer.

Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.

Abstract: A gear module includes a rotating cylinder, a first planetary gear set, a second planetary gear set, a concave-convex structure, and a limit bearing set. The first planetary gear set is accommodated in the rotating cylinder and includes a driven gear; the second planetary gear set includes a positioning frame, second planetary gears pivoted to a positioning frame, a driven gear engaged with the second planetary gears, and the positioning frame has a through hole; the concave-convex structure includes a convex column extended from the rotating cylinder and a concave hole formed on the positioning frame, the convex column is plugged into the concave hole; the limit bearing set includes a first ball bearing sheathing the driven gear and mounted between the driven gear and the through hole, and a second ball bearing sheathing the convex column and mounted between the convex column and the concave hole.

Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.

Abstract: A light-emitting device includes: a semiconductor stack, including a first semiconductor layer, an active region and a second semiconductor layer; a first contact electrode and a second contact electrode formed on the semiconductor stack, wherein the first contact electrode includes a first contact part formed on the first semiconductor layer and the second contact electrode includes a second contact part formed on the second semiconductor layer; an insulating stack formed on the semiconductor stack, including an opening on the second contact part; a first electrode pad and a second electrode pad formed on the insulating stack, wherein the second electrode pad filled in the opening and connecting the second contact part; wherein the second electrode pad includes an upper surface, and the upper surface includes a platform area and a depression area on the second contact part; wherein the platform area has a maximum height relative to other areas of the upper surface; wherein an area of a projection of the plat