Patents by Inventor Chun Wang

Chun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12247423
    Abstract: An electronic lock components includes a bracket configured to be mounted on a door panel and an electronic lock body configured to be assembled on or disassembled from the bracket. The bracket includes an elastic piece, and a portion of the elastic piece is inclined downward. The electronic lock body includes: a back cover body, having a through hole therethrough, in which when the back cover body is leaned against the bracket and then moved downward, one end of the portion of the elastic piece is able to be stuck in the through hole; and a main cover body, including a pushing piece having a convex portion facing the through hole, in which when the pushing piece is pushed toward the through hole, the convex portion is able to push the end of the portion of the elastic piece away from the through hole.
    Type: Grant
    Filed: February 9, 2023
    Date of Patent: March 11, 2025
    Assignee: Primax Electronics Ltd.
    Inventors: Li-Chun Wang, Meng-Chieh Liu
  • Publication number: 20250079550
    Abstract: A battery device includes a battery pack and multiple piezoelectric cooling units. A fixing seat of the battery pack has multiple accommodating grooves that are adjacent to each other. A heat dissipation channel is formed between two adjacent ones of the accommodating grooves. Multiple batteries of the battery pack are respectively accommodated in the accommodating grooves. Each of the piezoelectric cooling units corresponds in position to one of the heat dissipation channels, and includes a piezoelectric actuator module and a heat dissipation sheet. The piezoelectric actuator module is electrically coupled to an alternating voltage and can generate a mechanical vibration. A fixed end of the heat dissipation sheet is fixed on the piezoelectric actuator module. When the piezoelectric actuator module generates the mechanical vibration, a free end of the heat dissipation sheet is configured to swing and create an airflow that passes through the heat dissipation channel.
    Type: Application
    Filed: August 29, 2023
    Publication date: March 6, 2025
    Inventors: CHIH-KUN YANG, YU-CHUN WANG, JUI-YANG CHANG
  • Publication number: 20250080705
    Abstract: A projection device includes a light source module, a display panel, a freeform-surface reflective mirror, and a projection lens. The light source module includes a light source, a first Fresnel lens element, and a second Fresnel lens element. The first Fresnel lens element and the second Fresnel lens element are parallel to each other and located between the light source and the display panel. The display panel is arranged between the light source module and the freeform-surface reflective mirror. The projection lens is configured to transmit an image beam out of the projection device, and a direction of an optical axis of the projection lens is different from a direction of a normal of the first Fresnel lens element.
    Type: Application
    Filed: August 22, 2024
    Publication date: March 6, 2025
    Applicant: Coretronic Corporation
    Inventors: Kun-Zheng Lin, Wen-Chun Wang, Wei-Ting Wu, Wen-Chieh Chung, Jui-Chi Chen
  • Publication number: 20250074247
    Abstract: The present disclosure provides a smart pole charging system and a monitoring method. The database system initiates a configuration according to an original environmental status. The charging module is connected with an electric vehicle and provides the electrical energy to the electric vehicle. The monitoring module monitors a real-time environmental status around corresponding smart pole. The calculating module recognizes the real-time environmental status and outputs a calculation result. The router receives the calculation result. The cloud platform is communicated with the router and the database system. The router transmits the calculation result to the cloud platform through an open charge point protocol.
    Type: Application
    Filed: October 18, 2023
    Publication date: March 6, 2025
    Inventors: Ting-Chi Chang, Chun-Ta Chen, Che-Hsien Lien, Yu-Cheng Lee, Tien-Chun Wang, Chun-Wei Hu
  • Publication number: 20250079571
    Abstract: A thermal management module includes a substrate, a computing unit, a heat dissipation block, and at least one piezoelectric cooling unit. The computing unit is disposed on the substrate. A heating part of the computing unit is covered by the heat dissipation block, and the heat dissipation block can absorb heat energy generated by the computing unit. The piezoelectric cooling unit includes a piezoelectric actuator module and a heat dissipation sheet. The piezoelectric actuator module is disposed on the substrate. The piezoelectric actuator module is electrically coupled to an alternating voltage, and can generate a mechanical vibration. A fixed end of the heat dissipation sheet is fixed on the piezoelectric actuator module. When the piezoelectric actuator module generates the mechanical vibration, the free end can swing and create an airflow that passes through the heat dissipation block.
    Type: Application
    Filed: August 29, 2023
    Publication date: March 6, 2025
    Inventors: CHIH-KUN YANG, YU-CHUN WANG, JUI-YANG CHANG
  • Patent number: 12243907
    Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.
    Type: Grant
    Filed: January 5, 2024
    Date of Patent: March 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsuan-Han Tseng, Chun-Yuan Chen, Lu-Sheng Chou, Hsiao-Hui Tseng, Ching-Chun Wang
  • Patent number: 12237332
    Abstract: An integrated circuit is provided and includes first and second gates arranged in first and second layers, wherein the first and second gates extend in a first direction; a first insulating layer interposed between the first and second gates, wherein the first insulating layer, a first portion of the first gate, and a first portion of the second gate overlap with each other in a layout view; a cut layer, different from the first insulating layer, disposed on a second portion of the first gate; a first via passing through the cut layer and coupled to the second portion of the first gate; and a second via overlapping the first portion of the first gate and the first portion of the second gate, and coupled to the second gate. The first and second vias are configured to transmit different control signals to the first and second gates.
    Type: Grant
    Filed: June 28, 2023
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Guo-Huei Wu, Po-Chun Wang, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien
  • Publication number: 20250063772
    Abstract: A semiconductor structure including a substrate, a conductive layer, and a semiconductor device is provided. The substrate includes a first surface, a second surface opposite to the first surface, at least one insulating vacancy extending from the first surface toward the second surface, and a through hole passing through the substrate. The conductive layer fills in the through hole. The semiconductor device is disposed on the second surface and is electrically connected to the conductive layer, and the at least one insulating vacancy is distributed corresponding to the semiconductor device.
    Type: Application
    Filed: November 7, 2024
    Publication date: February 20, 2025
    Applicant: Industrial Technology Research Institute
    Inventors: Po-Chun Yeh, Hsiang-Chun Wang
  • Patent number: 12230593
    Abstract: A package structure is provided, including a substrate, a first passivation layer, a metallization layer, a second passivation layer, and a polymer layer. The first passivation layer is formed over the substrate. The metallization layer is conformally formed on the first passivation layer. The second passivation layer is conformally formed on the first passivation layer and the metallization layer. A step structure is formed on the top surface of the second passivation layer, and includes at least one lower part that is lower than the other parts of the step structure. The polymer layer is formed over the second passivation layer. A portion of the polymer layer extends into the lower part of the step structure to engage with the step structure.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Heng Chen, Pei-Haw Tsao, Shyue-Ter Leu, Rung-De Wang, Chien-Chun Wang
  • Publication number: 20250054600
    Abstract: This disclosure teaches the generation of multiple recipes for patients with chronic kidney disease. The recipes are generated by application of a large language model to patient data, including both medical and preference data. The recipes are verified by a dietician and may be used to generate shopping lists and instructions for an automated food preparation device.
    Type: Application
    Filed: August 8, 2024
    Publication date: February 13, 2025
    Applicant: Fresenius Medical Care Holdings Inc.
    Inventors: Peter Kotanko, Hanjie Zhang, Lin-Chun Wang, Ulrike Kotanko, Nancy Ginsberg
  • Publication number: 20250042292
    Abstract: A charging module configured to charge a plurality of electric vehicles through a plurality of charging piles is provided. The charging module includes a charging prediction mode and a charging scheduling unit. The charging prediction mode is obtained according to a plurality of historical charging data, wherein each historical charging data includes an actual charging amount and at least one of a stay time and a charging time. The charging scheduling unit is configured to obtain a predicted electricity demand and a predicted stay period of each electric vehicle through the charging prediction model; and generate a charging schedule including: providing each electric vehicle with a basic charging amount; and determining a charging priority of the electric vehicles according to the predicted electricity demand and the predicted stay period.
    Type: Application
    Filed: October 19, 2023
    Publication date: February 6, 2025
    Inventors: Zhiming ZHONG, Ken Weng KOW, Jing YANG, Tse-Chun WANG, Wei CIOU, Tsung-Hung TSAI, Ta-Wei HO
  • Patent number: 12218132
    Abstract: A method is provided and includes operations below: forming a multilayer stack, wherein the multilayer stack includes multiple first semiconductor layers and multiple second semiconductor layers that are alternately stacked; forming a first source region and a first drain region on opposing sides of a first portion of the multilayer stack and forming a second source region and a second drain region on opposing sides of a second portion of the multilayer stack; removing the second semiconductor layers in the multilayer stack; forming a first gate region, corresponding to a first transistor, over the first portion of the multilayer stack; forming a first insulating layer above the first gate region; and forming a second gate region, corresponding to a second transistor, above the first insulating layer and over the second portion of the multilayer stack.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Guo-Huei Wu, Po-Chun Wang, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien
  • Patent number: 12216366
    Abstract: Provided is a pixel structure. The pixel structure includes: a first electrode, a second electrode, and a liquid crystal layer that are disposed on one side of a substrate and successively stacked, wherein one of the first electrode and the second electrode is a pixel electrode and the other of the first electrode and the second electrode is a common electrode, and the second electrode includes a plurality of electrode branches sequentially arranged in a first direction, wherein each of the electrode branches includes a first end portion, a body portion, and a second end portion that are successively connected in a second direction, the body portion including at least one body segment.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: February 4, 2025
    Assignees: HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Qianqian Zhang, Chun Wang, Yuqi Liu, Hui Wang, Hongmei Yang, Wei Ren
  • Patent number: 12211876
    Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a semiconductor substrate having sidewalls that form one or more trenches. The one or more trenches are disposed along opposing sides of a photodiode and vertically extend from an upper surface of the semiconductor substrate to within the semiconductor substrate. A doped region is arranged along the upper surface of the semiconductor substrate and along opposing sides of the photodiode. A first dielectric lines the sidewalls of the semiconductor substrate and the upper surface of the semiconductor substrate. A second dielectric lines sidewalls and an upper surface of the first dielectric. The doped region has a width laterally between a side of the photodiode and a side of the first dielectric. The width of the doped region varies at different heights along the side of the photodiode.
    Type: Grant
    Filed: June 16, 2023
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yuan Chen, Ching-Chun Wang, Dun-Nian Yaung, Hsiao-Hui Tseng, Jhy-Jyi Sze, Shyh-Fann Ting, Tzu-Jui Wang, Yen-Ting Chiang, Yu-Jen Wang, Yuichiro Yamashita
  • Patent number: 12212800
    Abstract: A process for providing relevant video content to members of a communication group. When a triggering event to provide video content to a plurality of members of a communication group is detected, an electronic computing device assigns a reviewer rank to each one of the plurality of members of the communication group based on a user context associated with the respective members. The device then selects a member with the assigned reviewer rank higher than the respectively assigned reviewer ranks of other members and further transmits a notification to the member requesting permission to provide the video content to the members of the communication group. When a response indicating permission is received from the communication device associated with the selected member, the device provides the video content to the members associated with the communication group.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: January 28, 2025
    Assignee: MOTOROLA SOLUTIONS, INC.
    Inventors: Eric Johnson, Yujing Su, Chun Wang, Jeffrey Hirsch
  • Patent number: 12211701
    Abstract: A semiconductor device and method of manufacture are provided. In some embodiments a divergent ion beam is utilized to implant ions into a capping layer, wherein the capping layer is located over a first metal layer, a dielectric layer, and an interfacial layer over a semiconductor fin. The ions are then driven from the capping layer into one or more of the first metal layer, the dielectric layer, and the interfacial layer.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsan-Chun Wang, Chun-Feng Nieh
  • Patent number: 12210139
    Abstract: An optical photographing system includes eight lens elements which are, in order from an object side to an image side along an optical path: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element, a seventh lens element and an eighth lens element. Each of the eight lens elements has an object-side surface facing toward the object side and an image-side surface facing toward the image side. The object-side surface of the third lens element is concave in a paraxial region thereof. The fourth lens element has positive refractive power. The fifth lens element has positive refractive power. The sixth lens element has positive refractive power. The seventh lens element has negative refractive power, and the image-side surface of the seventh lens element is concave in a paraxial region thereof.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: January 28, 2025
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Kuan Chun Wang, Tzu-Chieh Kuo
  • Patent number: 12211843
    Abstract: A fin-type field effect transistor comprising a substrate, at least one gate stack and epitaxy material portions is described. The substrate has fins and insulators located between the fins, and the fins include channel portions and flank portions beside the channel portions. The at least one gate stack is disposed over the insulators and over the channel portions of the fins. The epitaxy material portions are disposed over the flank portions of the fins and at two opposite sides of the at least one gate stack. The epitaxy material portions disposed on the flank portions of the fins are separate from one another.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsiung Tsai, Ziwei Fang, Tsan-Chun Wang, Kei-Wei Chen
  • Publication number: 20250029589
    Abstract: An acoustic metasurface structure is configured to absorb sounds. The acoustic metasurface structure comprises a main body, an externally-connecting configuration and an inner configuration. The externally-connecting configuration and the inner configuration are respectively formed inside the main body. An externally-connecting tube of the externally-connecting configuration is in fluid communication with an external environment and an externally-connecting cavity of the externally-connecting configuration. An inner tube of the inner configuration is in fluid communication with the externally-connecting cavity and an inner cavity of the inner configuration. With the externally-connecting configuration and the inner configuration forming a series-type structure in the main body, the acoustic metasurface structure increases an acoustic impedance.
    Type: Application
    Filed: July 18, 2023
    Publication date: January 23, 2025
    Inventors: JUNG-SAN CHEN, TZU-HUEI KUO, WEI-CHUN WANG, WEN-YANG LO, CHENG-YI WANG
  • Patent number: D1064248
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: February 25, 2025
    Assignee: Delta Electronics, Inc.
    Inventors: Ming-Kai Hsieh, Ching-Hsiang Huang, Po-Chun Wang, Kuan-Ting Shen, Hao-Cheng Wang