Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first plurality of interconnects arranged within a first inter-level dielectric (ILD) structure on a first substrate, and a second plurality of interconnects arranged within a second ILD structure between the first ILD structure and a second substrate. A bonding structure is disposed within a recess extending through the second substrate. A connector structure is vertically between the first plurality of interconnects and the second plurality of interconnects. The second plurality of interconnects include a first interconnect directly contacting the bonding structure. The second plurality of interconnects also include one or more extensions extending from directly below the first interconnect to laterally outside of the first interconnect and directly above the connector structure, as viewed along a cross-sectional view.

Abstract: A paper-based micro-concentrator includes a bearing substrate, a fluid reservoir unit, a filter paper, an external electric field, an ion exchange membrane and a magnet. The fluid reservoir unit includes a first buffer solution tank and a second buffer solution tank, which are interval disposed on the bearing substrate. The filter paper is disposed on the bearing substrate, and two ends of the filter paper are respectively placed in the first buffer solution tank and the second buffer solution tank. The external electric field includes a cathode and an anode, which are respectively placed in the first buffer solution tank and the second buffer solution tank. The ion exchange membrane is disposed on the filter paper and close to the first buffer solution tank. The magnet is movably disposed under the bearing substrate.

Abstract: An integrated circuit is provided and includes first and second gates arranged in first and second layers, wherein the first and second gates extend in a first direction; a first insulating layer interposed between the first and second gates, wherein the first insulating layer, a first portion of the first gate, and a first portion of the second gate overlap with each other in a layout view; a cut layer, different from the first insulating layer, disposed on a second portion of the first gate; a first via passing through the cut layer and coupled to the second portion of the first gate; and a second via overlapping the first portion of the first gate and the first portion of the second gate, and coupled to the second gate. The first and second vias are configured to transmit different control signals to the first and second gates.

Abstract: Methods, systems and apparatuses, including computer programs encoded on computer storage media, are provided for generating prediction models related to targeting and acquiring customers. Thousands of variables of historical data, including data for prospects and external data, are used to train the prediction models. The variables are pre-processed, then sensitivity analysis is performed on the input variables with respect to the target. The variables with the most influence on the target are selected and added to the feature set used for training a prediction model.

Abstract: A viewing angle control device including a plurality of first polarizing portions and a plurality of transmissive portions is provided. The first polarizing portions are arranged along a first direction and extended in a second direction. The transmissive portions and the first polarizing portions are alternately arranged. Each of the first polarizing portions has a width in the first direction and a height in a direction perpendicular to the first direction and the second direction. A ratio of the height to the width of the first polarizing portion is greater than 1. A display apparatus adopting the viewing angle control device is also provided. The viewing angle control device and the display apparatus provided herein have a filter effect at a large viewing angle, improved light transmittance in the viewing angle direction, and excellent anti-peeping performance.

Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a semiconductor substrate having sidewalls that form one or more trenches. The one or more trenches are disposed along opposing sides of a photodiode and vertically extend from an upper surface of the semiconductor substrate to within the semiconductor substrate. A doped region is arranged along the upper surface of the semiconductor substrate and along opposing sides of the photodiode. A first dielectric lines the sidewalls of the semiconductor substrate and the upper surface of the semiconductor substrate. A second dielectric lines sidewalls and an upper surface of the first dielectric. The doped region has a width laterally between a side of the photodiode and a side of the first dielectric. The width of the doped region varyies at different heights along the side of the photodiode.

Abstract: The present invention proposes a data densifier comprising a plurality of first operation units and a second operation unit. The plurality of first operation units are respectively configured to be instantiated according to classification information, and the plurality of instantiated first operation units are configured to densify a plurality of sub data included in input data into a plurality of sub densified data. The second operation unit is configured to be instantiated according to the classification information, and the instantiated second operation unit is configured to merge the plurality of sub densified data from the plurality of first operation units into densified data. In addition, a data densification method used by the data densifier and a sense chip comprising the data densifier are also proposed.

Abstract: A lighting device includes a light board and a light dimmer circuit. The light board includes multiple first light emitting elements and second light emitting elements. The first light emitting elements are disposed in a first area of the light board. The second light emitting elements are disposed in a second area of the light board. The light dimmer circuit is configured to drive the second light emitting elements to generate flickering lights from the second area of the light board, and is configured to drive the first light emitting elements to generate non-flickering lights from the first area of the light board.

Abstract: Electronic device and camera module thereof are provided. Camera module includes lens, driving member, and photosensitive chip which is Bayer array sensor and includes pixel areas in rows and columns, and each pixel area includes four sub pixel areas. Lens is connected to driving member that can drive lens to switch between first position and second position relative to photosensitive chip. If lens is at first position, light incident from lens forms first image in first sub pixel area of photosensitive chip. If lens is at second position, light incident from lens forms second image in second sub pixel area of photosensitive chip. Content of first image is same as that of second image. Equivalent sub pixel areas of first and second sub pixel areas in one pixel area are any two sub pixel areas in the pixel area.

Abstract: A handheld device of compact size combining a mini electric vacuum/blower, a pencil sharpener, a rubbery eraser, and a storage unit. The inventive device has one or more containers that house a motor and rotary fan for the vacuum/blower, a battery that powers the vacuum/blower, a pencil sharpener, a rubbery eraser, and a storage unit. The vacuum is used to clean the crumbs from the rubbery eraser or other small objects on a surface, and the vacuum easily converts to a blower that will generate air steam. The storage unit can house certain sized school supplies such as crayons, pens, pencils, or other small items. The inventive of the device is compact enough so that it can be operated single handedly and it can be carried in pockets or small bags.

Abstract: A display device includes a multiple of light-emitting elements and a multiple of driving circuits. Each of the multiple of driving circuits is configured to generate a driving current to illuminate one of the multiple of light-emitting elements. Each of the multiple of driving circuits includes a first transistor, a second transistor, a reset circuit, a first control circuit and a second control circuit. The driving current flows from a first system high voltage terminal through the first transistor, the second transistor and one of the multiple of light-emitting elements to a system low voltage terminal. The first control circuit is configured to control the first transistor to modulate pulse amplitude of the driving current. The second control circuit is configured to control the second transistor to modulate pulse width of the driving current.

Abstract: A static identification area detecting method and module, chip, electronic device and medium, which can improve the accuracy of static identification area detection.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a contact layer over a metal silicide layer. The contact layer extends through a first dielectric structure. The semiconductor device structure includes a first metal nitride barrier layer over sidewalls of the contact layer. The first metal nitride barrier layer is directly adjacent to the first dielectric structure. The semiconductor device structure includes a second metal nitride barrier layer partially between the contact layer and the metal silicide layer and partially between the contact layer and the first metal nitride barrier layer. The metal silicide layer is below the first metal nitride barrier layer and the second metal nitride barrier layer.

Abstract: Null Data Packet Sounding for preamble punctured Physical Layer Convergence Procedure Protocol Data Unit (PPDU) for efficient use of a wireless channel bandwidth where a primary service co-exists.

Abstract: A method for manufacturing a semiconductor structure is provided. The method may include several operations. A piezoelectric capacitor is formed over a substrate, wherein the piezoelectric capacitor includes a metal electrode. An intermediate layer is formed on the metal electrode, and is patterned using a first mask layer as a mask. A metal layer is formed on the intermediate layer, wherein the metal layer electrically connects to the metal electrode. The metal layer is patterned using a second mask layer, wherein the intermediate layer is within a coverage area of the metal layer from a top-view perspective after the patterning of the metal layer. A semiconductor structure thereof is also provided.

Abstract: An image sensor structure that further includes a first substrate having a front side and a back side; a photodetector disposed on the front side of the first substrate and spanning a dimension Dp along a first direction; a gate electrode formed on the front side of the first substrate and partially overlapping the photodetector; a doped region as a floating diffusion region formed on the front side of the first substrate and disposed next to the photodetector; and an interconnect structure disposed on the front surface of the first substrate and overlying the gate electrode. The interconnect structure includes a second metal layer over a first metal layer, the second metal layer further includes a first and second metal features distanced a distance Ds along the first direction, the first metal feature is electrically connected to the doped feature, and a first ratio Ds/Dp is greater than 0.3.

Abstract: A latent code defined in an input space is processed by the mapping neural network to produce an intermediate latent code defined in an intermediate latent space. The intermediate latent code may be used as appearance vector that is processed by the synthesis neural network to generate an image. The appearance vector is a compressed encoding of data, such as video frames including a person's face, audio, and other data. Captured images may be converted into appearance vectors at a local device and transmitted to a remote device using much less bandwidth compared with transmitting the captured images. A synthesis neural network at the remote device reconstructs the images for display.

Abstract: A display device includes a light emitting unit, first and second capacitors, and first and second switches. The light emitting unit emits light according to a voltage level of a first node. A first terminal of the first capacitor is coupled to the first node, and a second terminal of the first capacitor is coupled to a second node. A first terminal of the second capacitor is coupled to the second node, and a second terminal of the first capacitor is coupled to the light emitting unit. A first terminal of the first switch is coupled to the first node, and a second terminal of the first switch is coupled to the light emitting unit. The second switch is configured to be turned on before the first switch is turned on, and a first terminal of the second switch is coupled to the first node.

Abstract: A photographing optical lens system includes seven lens elements which are, in order from an object side to an image side along an optical path: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element and a seventh lens element. Each of the seven lens elements has an object-side surface facing toward the object side and an image-side surface facing toward the image side. The object-side surface of the sixth lens element is concave in a paraxial region thereof, and the image-side surface of the sixth lens element is convex in a paraxial region thereof. At least one of the object-side surface and the image-side surface of at least one lens element of the photographing optical lens system has at least one inflection.

Abstract: A reference current/voltage generator includes a current mirror unit and a current-mode temperature compensation unit. The current mirror unit generates a first current, a first sum current and a second sum current flowing through first to third terminals thereof, and the first current, the first sum current and the second sum current are in a multiple relationship. The current-mode temperature compensation unit is electrically connected to the second and third terminals of the current mirror unit, and when a voltage on the second terminal is equal to a voltage on the third terminal, the first sum current is a sum of a current proportional to absolute temperature (PTAT) and a current complementary to absolute temperature (CTAT). The first terminal of the current mirror unit is an output terminal of the reference current/voltage generator and configured to output the first current as a reference current.