Patents by Inventor Chun Wang

Chun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120241
    Abstract: The present invention provides an electrostatic charge detecting packaging device comprising a carrier, multiple dies, and multiple electrostatic-charge-sensitive components; the carrier has a surface; the dies are mounted on the surface of the carrier; and the electrostatic-charge-sensitive components are mounted on the surface of the carrier; since an electrostatic voltage tolerance of each of the electrostatic-charge-sensitive components is lower than an electrostatic voltage tolerance of each of the dies, accumulated electrostatic charges are more likely to discharge towards the electrostatic-charge-sensitive components than towards the dies, and as such, by electrically testing whether the electrostatic-charge-sensitive components are functioning normally when packaging the dies, the present invention allows personnel to debug for knowing which packaging steps exactly cause more serious problems that lead to damaging electrostatic discharges in the dies.
    Type: Application
    Filed: November 30, 2022
    Publication date: April 11, 2024
    Inventors: Chung-Hsiung HO, Chien-Chun Wang, Li-Qiang Ye, Chi-Hsueh Li
  • Patent number: 11948949
    Abstract: In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yuan Chen, Ching-Chun Wang, Hsiao-Hui Tseng, Jen-Cheng Liu, Jhy-Jyi Sze, Shyh-Fann Ting, Wei Chuang Wu, Yen-Ting Chiang, Chia Ching Liao, Yen-Yu Chen
  • Patent number: 11944970
    Abstract: A microfluidic detection unit comprises at least one fluid injection section, a fluid storage section and a detection section. Each fluid injection section defines a fluid outlet; the fluid storage section is in gas communication with the atmosphere and defines a fluid inlet; the detection section defines a first end in communication with the fluid outlet and a second end in communication with the fluid inlet. A height difference is defined between the fluid outlet and the fluid inlet along the direction of gravity. When a first fluid is injected from the at least one fluid injection section, the first fluid is driven by gravity to pass through the detection section and accumulate to form a droplet at the fluid inlet, such that a state of fluid pressure equilibrium of the first fluid is established.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: April 2, 2024
    Assignees: INSTANT NANOBIOSENSORS, INC., INSTANT NANOBIOSENSORS CO., LTD.
    Inventors: Yu-Chung Huang, Yi-Li Sun, Ting-Chou Chang, Jhy-Wen Wu, Nan-Kuang Yao, Lai-Kwan Chau, Shau-Chun Wang, Ying Ting Chen
  • Patent number: 11948805
    Abstract: An etching method for selectively etching a silicon oxide film on a wafer surface that includes the silicon oxide film and a silicon nitride film includes: a surface layer removal process including: etching the silicon oxide film at a first etching rate and removing a surface modification layer covering on the silicon nitride film; and an etching process including: etching the silicon oxide film at a second etching rate. The first etching rate is smaller than the second etching rate.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: April 2, 2024
    Assignee: BEIJING NAURA MICROELECTRONICS EQUIPMENT CO., LTD.
    Inventors: Xin Wu, Chun Wang, Bo Zheng, Zhenguo Ma
  • Patent number: 11941298
    Abstract: A host system initiates an abort of a command that has been placed into a submission queue (SQ) of the host system. The host system identifies at least one of a first outcome and a second outcome. When the first outcome indicates that the command is not completed and the second outcome indicates that the SQ entry has been fetched from the SQ, the host system sends an abort request to a storage device, and issues a cleanup request to direct the host controller to reclaim host hardware resources allocated to the command. The host system adds a completion queue (CQ) entry to a CQ and sets an overall command status (OCS) value of the CQ entry based on at least one of the first outcome and the second outcome.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: March 26, 2024
    Assignee: MediaTek Inc.
    Inventors: Chih-Chieh Chou, Chia-Chun Wang, Liang-Yen Wang, Chin Chin Cheng, Szu-Chi Liu
  • Publication number: 20240094482
    Abstract: In some examples, an electronic device includes a light guide. In some examples, the light guide includes a facial side and a rear side. In some examples, the facial side includes a lens to focus incoming light. In some examples, the rear side includes exit features to guide outgoing light. In some examples, the electronic device includes an image sensor disposed behind the lens to capture the incoming light.
    Type: Application
    Filed: September 21, 2022
    Publication date: March 21, 2024
    Inventors: Super Liao, Xiao Jun Zhu, Hai Tao Liu, Hong Chun Wang
  • Publication number: 20240097090
    Abstract: A display device including at least two light source modules and a display control substrate is provided. Each of the at least two light source substrates has a first surface and a second surface opposite to each other and includes a plurality of light emitting elements and a plurality of connection pads. The light emitting elements are located on the second surface, and the connection pads are located on the first surface and are electrically connected to the light emitting elements. The display control substrate includes a back plate and a plurality of control elements. The control elements are located on the back plate, part of the control elements are electrically connected to the connection pads to drive and control the light emitting elements, and the second surface of each of the at least two light source substrates forms a part of a display surface of the display device.
    Type: Application
    Filed: September 13, 2023
    Publication date: March 21, 2024
    Applicant: Coretronic Corporation
    Inventors: Ming-Chuan Chih, Wen-Chun Wang, Chun-Chi Hsu, Bo-Chih Pan, Yu-Wei Liang
  • Publication number: 20240095989
    Abstract: Apparatuses, systems, and techniques to generate a video using two or more images comprising objects to be included in the video. In at least one embodiment, objects are identified in two or more images using one or more neural networks, to generate a video to include the objects in the video.
    Type: Application
    Filed: September 15, 2022
    Publication date: March 21, 2024
    Inventors: Arun Mohanray Mallya, Ting-Chun Wang, Ming-Yu Liu
  • Publication number: 20240093357
    Abstract: A semiconductor device is manufactured by modifying an electromagnetic field within a deposition chamber. In embodiments in which the deposition process is a sputtering process, the electromagnetic field may be modified by adjusting a distance between a first coil and a mounting platform. In other embodiments, the electromagnetic field may be adjusted by applying or removing power from additional coils that are also present.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 21, 2024
    Inventors: Jen-Chun Wang, Ya-Lien Lee, Chih-Chien Chi, Hung-Wen Su
  • Patent number: 11934959
    Abstract: Apparatuses, systems, and techniques are presented to synthesize consistent images or video. In at least one embodiment, one or more neural networks are used to generate one or more second images based, at least in part, on one or more point cloud representations of one or more first images.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: March 19, 2024
    Assignee: NVIDIA CORPORATION
    Inventors: Arun Mallya, Ting-Chun Wang, Ming-Yu Liu, Karan Sapra
  • Patent number: 11933999
    Abstract: An optical structure film and a light source module are provided. The optical structure film includes multiple optical unit microstructures. Each of the optical unit microstructures has four side surfaces and an inwardly concave beam splitting surface. The beam splitting surface is respectively connected to the side surfaces, and the beam splitting surface has four endpoints when viewed from a front viewing angle. Connection lines of the four endpoints form a rectangle. The beam splitting surface includes at least one beam splitting curved surface. A junction of the at least one beam splitting curved surface and one of the four side surfaces is a first line segment. A projection of a midpoint of an edge of the rectangle on the beam splitting surface overlaps with a relative extreme point of the first line segment.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: March 19, 2024
    Assignee: Coretronic Corporation
    Inventors: Wen-Chun Wang, Chih-Jen Tsang, Chung-Wei Huang
  • Patent number: 11929328
    Abstract: A semiconductor device includes a transistor having a source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from one another.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yang Wu, Shiu-Ko JangJian, Ting-Chun Wang, Yung-Si Yu
  • Publication number: 20240079332
    Abstract: A semiconductor device includes a transistor having a source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from one another.
    Type: Application
    Filed: November 8, 2023
    Publication date: March 7, 2024
    Inventors: Chia-Yang Wu, Shiu-Ko JangJian, Ting-Chun Wang, Yung-Si Yu
  • Patent number: 11921543
    Abstract: A system and method of docking an information handling system to an intelligent wireless fan dock comprising a docking sensor to detect a docking event, a wireless module to establish a wireless link of the intelligent wireless fan dock with the docked information handling system upon detection of a docking event and to receive a dynamic fan speed request command to adjust extended fan cooling airflow from fan dock control system operating at the docked information handling system, where the fan dock control system has determined that the docked information handling system and the intelligent wireless fan dock pairing enables an increased performance mode and altered power draw limitations for the docked information handling system relative to the information handling system in an undocked state, and increasing the extended fan cooling airflow of a cooling fan based on the dynamic fan speed request command from the docked information handling system.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: March 5, 2024
    Assignee: Dell Products, LP
    Inventors: Lee-Ching Kuo, Hong Ling Chen, Hou Chun Wang, En-Yu Jen, Chen-Yu Lin
  • Publication number: 20240073773
    Abstract: Various techniques and schemes pertaining to extremely-high throughput (EHT) multi-link maximum channel switching in wireless communications are described. A station (STA) multi-link device (MLD) receives an indication from a reporting access point (AP) affiliated with an AP MLD on one link of multiple links. The STA MLD determines a channel switching time when a reported AP switches from operating in a current channel of the reported AP to operating in a new channel on one other link of the multiple links based on the indication.
    Type: Application
    Filed: August 16, 2023
    Publication date: February 29, 2024
    Inventors: Yongho Seok, Chao-Chun Wang, Kai Ying Lu, James Chih-Shi Yee, Gabor Bajko
  • Publication number: 20240071758
    Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a gate electrode layer on the p-type semiconductor layer, and patterning the gate electrode layer to form a gate electrode. Preferably, the gate electrode includes an inclined sidewall.
    Type: Application
    Filed: September 23, 2022
    Publication date: February 29, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Tung Yeh, You-Jia Chang, Bo-Yu Chen, Yun-Chun Wang, Ruey-Chyr Lee, Wen-Jung Liao
  • Publication number: 20240072128
    Abstract: A method of forming a semiconductor device includes forming a source/drain region and a gate electrode adjacent the source/drain region, forming a hard mask over the gate electrode, forming a bottom mask over the source/drain region, wherein the gate electrode is exposed, and performing a nitridation process on the hard mask over the gate electrode. The bottom mask remains over the source/drain region during the nitridation process and is removed after the nitridation. The method further includes forming a silicide over the source/drain region after removing the bottom mask.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Inventors: Tsan-Chun Wang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11916058
    Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Lun Chien, Po-Chun Wang, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien
  • Patent number: 11916100
    Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsuan-Han Tseng, Chun-Yuan Chen, Lu-Sheng Chou, Hsiao-Hui Tseng, Ching-Chun Wang
  • Patent number: D1017295
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: March 12, 2024
    Assignee: Nonet Inc.
    Inventors: Beico Chiu, Yi-Chun Wang, Xiang-Yi Zhan