Patents by Inventor Chun-Wei Chang
Chun-Wei Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250116941Abstract: A stitching method for an exposure process includes following steps. A wafer is provided. The wafer includes interposer regions, each of which includes a logic chip region, a first memory chip region, and a second memory chip region. The logic chip region is located between the first and second memory chip regions. A photoresist layer is formed on the wafer. First exposure processes are performed on the photoresist layer by applying a first photomask to form first shot regions in the photoresist layer. Second exposure processes are performed on the photoresist layer by applying a second photomask to form second shot regions in the photoresist layer. The first shot regions and the second shot regions are arranged alternately in a first direction. The first shot regions and the second shot regions are overlapped to form stitching regions, each of which is not located in the logic chip region.Type: ApplicationFiled: November 14, 2023Publication date: April 10, 2025Applicants: Powerchip Semiconductor Manufacturing Corporation, AP Memory Technology CorporationInventors: Shou-Zen Chang, Chun-Lin Lu, Cheng-Shu Ho, Kuo-Wei Liu, Kee-Wei Chung, Ru-Yi Cai
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Patent number: 12272741Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first semiconductor layer overlying a substrate. A first barrier layer is disposed on the first semiconductor layer. A second semiconductor layer overlies and directly contacts the first barrier layer. A second barrier layer directly contacts the first barrier layer. A third semiconductor layer overlies the second barrier layer. A fourth semiconductor layer overlies the third semiconductor layer. Outer sidewalls of the third semiconductor layer, outer sidewalls of the fourth semiconductor layer, and outer sidewalls of the second barrier layer are respectively aligned.Type: GrantFiled: August 3, 2023Date of Patent: April 8, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Man-Ho Kwan, Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Ting-Fu Chang
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Patent number: 12272592Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.Type: GrantFiled: May 15, 2024Date of Patent: April 8, 2025Assignee: RICHTEK TECHNOLOGY CORPORATIONInventors: Kun-Huang Yu, Chien-Yu Chen, Ting-Wei Liao, Chih-Wen Hsiung, Chun-Lung Chang, Kuo-Chin Chiu, Wu-Te Weng, Chien-Wei Chiu, Yong-Zhong Hu, Ta-Yung Yang
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Patent number: 12271019Abstract: A backlight module includes a light source, a first prism sheet disposed on the light source, and a light type adjustment sheet disposed on a side of the first prism sheet away from the light source and including a base and multiple light type adjustment structures. The multiple light type adjustment structures are disposed on the first surface of the base. Each light type adjustment structure has a first structure surface and a second structure surface connected to each other. The first structure surface of each light type adjustment structure and the first surface of the base form a first base angle therebetween, and the second structure surface of each light type adjustment structure and the first surface of the base form a second base angle therebetween. The angle of the first base angle is different from the angle of the second base angle.Type: GrantFiled: October 2, 2023Date of Patent: April 8, 2025Assignee: Coretronic CorporationInventors: Chih-Jen Tsang, Chung-Wei Huang, Shih-Yen Cheng, Jung-Wei Chang, Han-Yuan Liu, Chun-Wei Lee
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Publication number: 20250102580Abstract: A calibration system and a calibration method for state of charge (SOC) and state of health (SOH) in an energy storage system are provided. The calibration system includes a Main Battery Management System (MBMS) and a plurality of racks, wherein, when the MBMS determines that one of the plurality of racks meets auto-calibration conditions, the MBMS utilizes a battery feature value extraction algorithm to obtain feature value data of each of battery packs, and predicts the number of battery cycles for each of the battery packs via a battery aging correction model. In this way, the SOC and the SOH for each of the battery packs can be accurately calculated, so that maintenance personnel can clearly comprehend the status of each of the racks, thereby improving the efficiency of power management.Type: ApplicationFiled: January 22, 2024Publication date: March 27, 2025Applicant: SIMPLO TECHNOLOGY CO., LTD.Inventors: Ya-Mei CHANG, Chi-Yang CHENG, Chun-Chang CHEN, Chia-Wei CHEN
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Publication number: 20250096022Abstract: A semiconductor manufacturing system includes: a nozzle including a first channel that allows a fluid to flow through; a light source configured to emit light; and a light sensor configured to receive light, the light source and the light sensor being disposed within the first channel and opposite to each other. The semiconductor manufacturing system is configured to: emit light, by the light source, from within the nozzle toward a surface while the nozzle is dispensing the fluid; receive the light reflected from the surface by the light sensor, the emitted light and the reflected light adapted to be contained within the fluid; and examine a status of the reflected light. The emitted light and the reflected light propagate in a direction parallel to a longitudinal axis of the first channel.Type: ApplicationFiled: December 5, 2024Publication date: March 20, 2025Inventors: KAI-LIN CHUANG, TSUNG-CHI CHEN, PEI-JUNG CHANG, CHUN-WEI HUANG, JUN XIU LIU
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Patent number: 12249542Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.Type: GrantFiled: November 17, 2023Date of Patent: March 11, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hao Kung, Chih-Chieh Chang, Kao-Feng Liao, Hui-Chi Huang, Kei-Wei Chen
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Publication number: 20250074247Abstract: The present disclosure provides a smart pole charging system and a monitoring method. The database system initiates a configuration according to an original environmental status. The charging module is connected with an electric vehicle and provides the electrical energy to the electric vehicle. The monitoring module monitors a real-time environmental status around corresponding smart pole. The calculating module recognizes the real-time environmental status and outputs a calculation result. The router receives the calculation result. The cloud platform is communicated with the router and the database system. The router transmits the calculation result to the cloud platform through an open charge point protocol.Type: ApplicationFiled: October 18, 2023Publication date: March 6, 2025Inventors: Ting-Chi Chang, Chun-Ta Chen, Che-Hsien Lien, Yu-Cheng Lee, Tien-Chun Wang, Chun-Wei Hu
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Publication number: 20250081730Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.Type: ApplicationFiled: June 26, 2024Publication date: March 6, 2025Inventors: Andrew Lin, Alper Ozgurluk, Chao Liang Chien, Cheuk Chi Lo, Chia-Yu Chen, Chien-Chung Wang, Chih Pang Chang, Chih-Hung Yu, Chih-Wei Chang, Chin Wei Hsu, ChinWei Hu, Chun-Kai Tzeng, Chun-Ming Tang, Chun-Yao Huang, Hung-Che Ting, Jung Yen Huang, Lungpao Hsin, Shih Chang Chang, Tien-Pei Chou, Wen Sheng Lo, Yu-Wen Liu, Yung Da Lai
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Publication number: 20250079308Abstract: An electronic device is disclosed. The electronic device includes a first electronic component and a first interposer. The first electronic component is disposed under the interposer and includes a logic circuit and a power delivery circuit disposed between the interposer and the logic circuit. The interposer and the power delivery circuit are collectively configured to function as a power delivery structure which is electrically connected to the logic circuit.Type: ApplicationFiled: August 29, 2023Publication date: March 6, 2025Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hao-Chih HSIEH, Chun-Kai CHANG, Chao Wei LIU
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Publication number: 20250066899Abstract: A method includes: positioning a wafer on an electrostatic chuck of a physical vapor deposition apparatus, the wafer including an opening exposing a conductive feature; setting a temperature of the wafer to a room temperature; forming a tungsten thin film in the opening by the physical vapor deposition apparatus, the tungsten thin film including a bottom portion that is on an upper surface of the conductive feature exposed by the opening, a top portion that is on an upper surface of a dielectric layer through which the opening extends and a sidewall portion that is on a sidewall of the dielectric layer exposed by the opening; removing the top portion and the sidewall portion of the tungsten thin film from over the opening; and forming a tungsten plug in the opening on the bottom portion by selectively depositing tungsten by a chemical vapor deposition operation.Type: ApplicationFiled: August 23, 2023Publication date: February 27, 2025Inventors: Chun-Yen LIAO, I. LEE, Shu-Lan CHANG, Sheng-Hsuan LIN, Feng-Yu CHANG, Wei-Jung LIN, Chun-I TSAI, Chih-Chien CHI, Ming-Hsing TSAI, Pei Shan CHANG, Chih-Wei CHANG
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Patent number: 12235409Abstract: An optical lens assembly includes, from an object side to an image side, at least four optical lens elements. At least one of the at least four optical lens elements includes an anti-reflective coating. The at least one optical lens element including the anti-reflective coating is made of a plastic material. The anti-reflective coating is arranged on an object-side surface or an image-side surface of the at least one optical lens element including the anti-reflective coating. The anti-reflective coating includes at least one coating layer. One of the at least one coating layer at the outer of the anti-reflective coating is made of ceramics. The anti-reflective coating includes a plurality of holes, and sizes of the plurality of holes adjacent to the outer of the anti-reflective coating are larger than sizes of the plurality of holes adjacent to the inner of the anti-reflective coating.Type: GrantFiled: December 17, 2021Date of Patent: February 25, 2025Assignee: LARGAN PRECISION CO., LTD.Inventors: Wen-Yu Tsai, Chien-Pang Chang, Chi-Wei Chi, Wei-Fong Hong, Chun-Hung Teng, Kuo-Chiang Chu
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Patent number: 12235410Abstract: An optical lens assembly includes, from an object side to an image side, at least four optical lens elements. At least one of the at least four optical lens elements includes an anti-reflective coating. The at least one optical lens element including the anti-reflective coating is made of a plastic material. The anti-reflective coating is arranged on an object-side surface or an image-side surface of the at least one optical lens element including the anti-reflective coating. The anti-reflective coating includes at least one coating layer. One of the at least one coating layer at the outer of the anti-reflective coating is made of ceramics. The anti-reflective coating includes a plurality of holes, and sizes of the plurality of holes adjacent to the outer of the anti-reflective coating are larger than sizes of the plurality of holes adjacent to the inner of the anti-reflective coating.Type: GrantFiled: January 17, 2022Date of Patent: February 25, 2025Assignee: LARGAN PRECISION CO., LTD.Inventors: Wen-Yu Tsai, Chien-Pang Chang, Chi-Wei Chi, Wei-Fong Hong, Chun-Hung Teng, Kuo-Chiang Chu
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Patent number: 12219123Abstract: A method for rendering data of a three-dimensional image adapted to an eye position and a display system are provided. The method is used to render the three-dimensional image to be displayed in a three-dimensional space. In the method, a three-dimensional image data used to describe the three-dimensional image is obtained. The eye position of a user is detected. The ray-tracing information between the eye position and each lens unit of a multi-optical element module forms a region of visibility (RoV) that may cover a portion of the three-dimensional image in the three-dimensional space. When coordinating the physical characteristics of a display panel and the multi-optical element module, a plurality of elemental images can be obtained. The elemental images form an integral image that records the three-dimensional image data adapted to the eye position, and the integral image is used to reconstruct the three-dimensional image.Type: GrantFiled: July 8, 2021Date of Patent: February 4, 2025Assignee: LIXEL INC.Inventors: Chun-Hsiang Yang, Chih-Hung Ting, Kai-Chieh Chang, Hsin-You Hou, Chih-Wei Shih, Wei-An Chen, Kuan-Yu Chen
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Publication number: 20250019684Abstract: A method for maintaining lamellar structure of cell, configured to manufacture a lamellar cell product, comprises the following steps of: seeding a predetermined number of cells in a culture device containing a first culture medium and culturing the predetermined number of cells for a predetermined time to form a cell planar structure; placing a mold in the culture device to cover at least an outer portion of the cell planar structure; adding a gel into the culture device with the mold to envelop the cell planar structure; and separating the gel and the cell planar structure enveloped therein from the culture device and the mold to form the lamellar cell product.Type: ApplicationFiled: July 5, 2024Publication date: January 16, 2025Inventors: Hong-Nerng Ho, Heng-Yu Liu, Chen-Wei Lan, Chung-Wei Chang, Bo-He Chen, Chui Wei Wong, Chun-Lin Liu
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Publication number: 20250015246Abstract: A semiconductor device is provided, which includes an active region, a first semiconductor layer, a first metal element-containing structure, a first p-type or n-type layer, a second semiconductor layer and an insulating layer. The active region has a first surface and a second surface. The first semiconductor layer is at the first surface. The first metal element-containing structure covers the first semiconductor layer and comprising a first metal element. The first p-type or n-type layer is between the first semiconductor layer and the first metal element-containing structure. The second semiconductor layer is between the first semiconductor layer and the first p-type or n-type layer. The insulating layer covers a portion of the first semiconductor layer and a portion of the second semiconductor. The first p-type or n-type layer includes an oxygen element (O) and a second metal element and has a thickness less than or equal to 20 nm.Type: ApplicationFiled: September 23, 2024Publication date: January 9, 2025Inventors: Yu-Tsu LEE, Yi-Yang CHIU, Chun-Wei CHANG, Min-Hao YANG, Wei-Jen HSUEH, Yi-Ming CHEN, Shih-Chang LEE, Chung-Hao WANG
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Publication number: 20240421537Abstract: The present invention relates to a lockable connector assembly, including a wire-end connector and a board-end connector. The wire-end connector includes a first body and a locking member. The first body has a flexible positioning member and a side guide groove. The locking member is movably disposed in the side guide groove. When the locking member is located in an initial position, the wire-end connector is capable of being engaged with the board-end connector. When the locking member is moved from the initial position to an insertion position, the locking member is abutted against the flexible positioning member so that the flexible positioning member is fixedly disposed in the locked position.Type: ApplicationFiled: January 17, 2024Publication date: December 19, 2024Inventors: Hsien-Chang LIN, Chun-Wei CHANG
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Patent number: D1062545Type: GrantFiled: May 7, 2023Date of Patent: February 18, 2025Assignees: Acer Incorporated, Acer Gadget Inc.Inventors: Yun Cheng, Ker-Wei Lin, Hao-Ming Chang, Chun-Ta Chen, Wei-Chen Lee, Chih-Yuan Chang
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Patent number: D1063712Type: GrantFiled: May 7, 2023Date of Patent: February 25, 2025Assignees: Acer Incorporated, Acer Gadget Inc.Inventors: Yun Cheng, Ker-Wei Lin, Hao-Ming Chang, Chun-Ta Chen, Wei-Chen Lee, Chih-Yuan Chang
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Patent number: D1067795Type: GrantFiled: March 20, 2023Date of Patent: March 25, 2025Assignee: HONG-MING TECHNOLOGY CO., LTD.Inventor: Chun Wei Chang