Abstract: A method for maintaining lamellar structure of cell, configured to manufacture a lamellar cell product, comprises the following steps of: seeding a predetermined number of cells in a culture device containing a first culture medium and culturing the predetermined number of cells for a predetermined time to form a cell planar structure; placing a mold in the culture device to cover at least an outer portion of the cell planar structure; adding a gel into the culture device with the mold to envelop the cell planar structure; and separating the gel and the cell planar structure enveloped therein from the culture device and the mold to form the lamellar cell product.

Abstract: A semiconductor device is provided, which includes an active region, a first semiconductor layer, a first metal element-containing structure, a first p-type or n-type layer, a second semiconductor layer and an insulating layer. The active region has a first surface and a second surface. The first semiconductor layer is at the first surface. The first metal element-containing structure covers the first semiconductor layer and comprising a first metal element. The first p-type or n-type layer is between the first semiconductor layer and the first metal element-containing structure. The second semiconductor layer is between the first semiconductor layer and the first p-type or n-type layer. The insulating layer covers a portion of the first semiconductor layer and a portion of the second semiconductor. The first p-type or n-type layer includes an oxygen element (O) and a second metal element and has a thickness less than or equal to 20 nm.

Abstract: The present invention relates to a lockable connector assembly, including a wire-end connector and a board-end connector. The wire-end connector includes a first body and a locking member. The first body has a flexible positioning member and a side guide groove. The locking member is movably disposed in the side guide groove. When the locking member is located in an initial position, the wire-end connector is capable of being engaged with the board-end connector. When the locking member is moved from the initial position to an insertion position, the locking member is abutted against the flexible positioning member so that the flexible positioning member is fixedly disposed in the locked position.

Abstract: A method for obtaining a heart rate value by an optical sensing apparatus includes: receiving, by a first calculator in a processor and from a light receiver, a PPG signal; receiving, by a second calculator in the processor and from a motion sensor, a motion signal; determining, by the first calculator, a first heart rate value; determining, by the first calculator, a validity indicator according to the PPG signal; and determining, by the second calculator, a second heart rate value according to the PPG signal and the motion signal. When the validity indicator is determined to satisfy a predetermined requirement, the processor outputs the first heart rate value as the heart rate value. When the validity indicator is determined to not satisfy the predetermined requirement, the processor outputs the second heart rate value as the heart rate value.

Abstract: A semiconductor device includes a semiconductor stack, a reflective structure, and a conductive structure. The semiconductor stack includes a first semiconductor structure, a second semiconductor structure and an active region located between the first semiconductor structure and the second semiconductor structure. The reflective structure is located at a side of semiconductor stack closed to the first semiconductor structure, and includes a first metal. The conductive structure locates between the reflective structure and the first semiconductor structure, and includes a first region overlapping with the active structure and a second region which does not overlap with the active structure. The first metal in the second region has a concentration smaller than 5 atomic percent.

Abstract: A semiconductor structure includes a substrate, a through via penetrating the substrate, a trench capacitor, a first RDL, a second RDL, a contact feature, and a chip. The trench capacitor extends from a back surface toward a front surface of the substrate, wherein the trench capacitor is separated from an active area at the front surface of the substrate. The first RDL is disposed over the front surface and electrically connecting to the through via. The second RDL is disposed over the back surface of the substrate and electrically connecting to the through via and the trench capacitor. The contact feature is disposed over the second RDL and electrically connecting to the trench capacitor through the second RDL. The chip is bonded over the front surface of the substrate. A method of manufacturing the semiconductor structure is also provided.

Abstract: An electromigration (EM) sign-off methodology that utilizes a system for analyzing an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes a memory and a processor configured for calculating adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat dissipating elements located within a defined thermal coupling volume or range of the heat sensitive structures.

Abstract: The connector assembly for a seat belt comprises a wire-end connector and a board-end connector. The wire-end connector and the board-end connector are respectively designed to form an integral structure of the shell and internal components using stoppers and hooks. When the wire-end connector is fitted with the board-end connector in a fitting direction, they are engaged with each other, thereby preventing relative movement in the fitting direction. The connector assembly further includes a multi-level waterproof design for preventing the connector assembly and the circuit board from moisture damage.

Abstract: A method includes bonding a first package component on a composite carrier, and performing a first polishing process on the composite carrier to remove a base carrier of the composite carrier. The first polishing process stops on a first layer of the composite carrier. A second polishing process is performed to remove the first layer of the composite carrier. The second polishing process stops on a second layer of the composite carrier. A third polishing process is performed to remove a plurality of layers in the composite carrier. The plurality of layers include the second layer, and the third polishing process stops on a dielectric layer in the first package component.

Abstract: Implantation mask formation techniques described herein include increasing an initial aspect ratio of a pattern in an implantation mask by non-lithography techniques, which may include forming a resist hardening layer on the implantation mask. The pattern may be formed by photolithography techniques to the initial aspect ratio that reduces or minimizes the likelihood of pattern collapse during formation of the pattern. Then, the resist hardening layer is formed on the implantation mask to increase the height of the pattern and reduce the width of the pattern, which increases the aspect ratio between the height of the openings or trenches and the width of the openings or trenches of the pattern. In this way, the pattern in the implantation mask may be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the likelihood of pattern collapse during formation of the pattern.

Abstract: A connector assembly comprises a wire end connector, a board end connector, and an operating element. The board end connector includes a base and an extending tube body, which laterally forms a protrusion. The wire end connector includes a body and a wire connecting portion. The body has a shell that forms a guide groove and a side hole. The operating element has a pivot portion, a first extending arm, and a second extending arm. When the board end connector and the wire end connector are in an initial state and the operating element is in an unlocked position, the second extending arm is away from the guide groove. When the board end connector and the wire end connector are switched to a mating state, the protrusion contacts the first extending arm, causing the operating element to rotate from the unlocked position to a locked position.

Abstract: A quick-change vice base with improved structure, which comprises: a base body, a quick-change coupler, a moveable block set and a central bolt, wherein, the bottoms of the first moveable block and second moveable block are respectively locked with a moveable block positioning base, one end of the moveable block positioning base has a pushing block; when the lead screw rotates clockwise, the first moveable block and the second moveable block will move toward the quick-change coupler, so that the curved stopping blocks on the first moveable block and the second moveable block will be fitted into the recesses of the quick-change coupler; when the lead screw rotates anticlockwise, the first movable block and the second movable block will move away from the quick-change coupler and drive the moveable block positioning seat to move simultaneously.

Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a package structure. The package structure includes a passivation layer formed over an interconnect structure; an electrically-conductive structure formed on the passivation layer and extending through the passivation layer to electrically contact the interconnect structure; a dielectric structure formed over the passivation layer and surrounding the electrically-conductive structure to expose at least a portion of a top surface of the electrically-conductive structure; and a metallic protection structure formed on the top surface of the electrically-conductive structure exposed from the dielectric structure. The top surface of the metallic protection structure is aligned with or lower than a top surface of the dielectric structure.

Abstract: A semiconductor device is provided, which includes a semiconductor stack and a first contact structure. The semiconductor stack includes an active layer and has a first surface and a second surface. The first contact structure is located on the first surface and includes a first semiconductor layer, a first metal element-containing structure and a first p-type or n-type layer. The first metal element-containing structure includes a first metal element. The first p-type or n-type layer physically contacts the first semiconductor layer and the first metal element-containing structure. The first p-type or n-type layer includes an oxygen element (O) and a second metal element and has a thickness less than or equal to 20 nm, and the first semiconductor layer includes a phosphide compound or an arsenide compound.

Abstract: An electromigration (EM) sign-off methodology that utilizes a system for analyzing an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes a memory and a processor configured for calculating adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat dissipating elements located within a defined thermal coupling volume or range of the heat sensitive structures.

Abstract: Implantation mask formation techniques described herein include increasing an initial aspect ratio of a pattern in an implantation mask by non-lithography techniques, which may include forming a resist hardening layer on the implantation mask. The pattern may be formed by photolithography techniques to the initial aspect ratio that reduces or minimizes the likelihood of pattern collapse during formation of the pattern. Then, the resist hardening layer is formed on the implantation mask to increase the height of the pattern and reduce the width of the pattern, which increases the aspect ratio between the height of the openings or trenches and the width of the openings or trenches of the pattern. In this way, the pattern in the implantation mask may be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the likelihood of pattern collapse during formation of the pattern.

Abstract: In some embodiments, the present disclosure relates to an image sensor integrated chip. The image sensor integrated chip includes a floating diffusion node disposed within a substrate. A plurality of photodetectors are disposed around the floating diffusion node, as viewed in a plan-view, and a plurality of transfer transistor gates are disposed between the floating diffusion node and the plurality of photodetectors, as viewed in the plan-view. One or more transistor gates are disposed on the substrate. A device isolation structure extends in a closed loop around the one or more transistor gates. The device isolation structure is laterally offset from the floating diffusion node.

Abstract: A semiconductor structure includes a plurality of dies over a redistribution layer (RDL). A first die comprises: a first substrate; a first (RDL), disposed over a front surface of the first substrate; and a first back-side through via (BSTV), extending from a back surface of the first substrate toward the front surface of the first substrate. A second die, adjacent to the first die and separated from the first die by a molding material, comprises: a second substrate; a second RDL, disposed over a front surface of the second substrate; and a second BSTV, extending from a back surface of the second substrate toward the front surface of the second substrate. The RDL continuously covers the back surfaces of the first and second substrates, and electrically connects the first RDL to the second RDL via the first and second BSTVs. A method of manufacturing the semiconductor structure is also provided.

Abstract: A semiconductor structure includes a substrate, a through via penetrating the substrate, a trench capacitor, a first redistribution layer (RDL), a second RDL, and a contact feature. The trench capacitor extends from a back surface toward a front surface of the substrate, wherein the trench capacitor is separated from an active area at the front surface of the substrate. The first RDL is disposed over the front surface and electrically connecting to the through via, wherein the active area is disposed between the trench capacitor and the first RDL. The second RDL is disposed over the back surface and electrically connecting to the through via and the trench capacitor. The contact feature is disposed over the first RDL and electrically connecting to the trench capacitor through the first RDL, the through via and the second RDL. A method of manufacturing the semiconductor structure is also provided.

Abstract: The invention provides an easy lock connector with unlock structure applied to a flat wire and a circuit board. The flat wire has a notch and a ground wire on the two sides of a head end respectively. The easy-lock connector includes an upper housing, a lower housing, a rubber core and a terminal. After the notch of the flat wire is buckled by a stopper of the lower housing, by pressing a pressing member of the upper housing, the pressing member applies an external force to an elastic member of the lower housing to deform the elastic member. An extension arm of the lower housing is linked by the elastic member to cause the stopper to act in one direction so as to release the state of the stopper from locking the gap. In another embodiment, the easy-lock connector can also achieve an electromagnetic shielding effect by adding a shielding iron shell.