Abstract: An optical lens assembly includes, from an object side to an image side, at least four optical lens elements. At least one of the at least four optical lens elements includes an anti-reflective coating. The at least one optical lens element including the anti-reflective coating is made of a plastic material. The anti-reflective coating is arranged on an object-side surface or an image-side surface of the at least one optical lens element including the anti-reflective coating. The anti-reflective coating includes at least one coating layer. One of the at least one coating layer at the outer of the anti-reflective coating is made of ceramics. The anti-reflective coating includes a plurality of holes, and sizes of the plurality of holes adjacent to the outer of the anti-reflective coating are larger than sizes of the plurality of holes adjacent to the inner of the anti-reflective coating.

Abstract: Methods, systems, and devices for top die back-side marking for memory systems are described. One or more alignment marks may be added to the back-side of a top memory die in a multi-layer memory device and used to align a position of the top memory die relative to a position of a memory die below the top memory die. The alignment marks may be formed on the top memory die during the manufacturing process of the multi-layer memory device. Operations for forming the alignment marks are described using various semiconductor fabrication techniques. Operations are also disclosed for using the alignment marks to modify placement of the top memory die to reduce the alignment offset in the manufacturing process of subsequent memory dies.

Abstract: A method for creating a layout element includes receiving an integrated circuit (IC) layout pattern that includes a shape corresponding to a component of the layout pattern. A mathematical definition of the shape is retrieved from a shape database, and parameter inputs regarding characteristics of the shape are received. A vertex listing is created based on the mathematical definition of the shape and the parameter inputs, and a layout element is created based on the vertex listing.

Abstract: A lock device structure includes an assembly of a case body and an actuator body, a linking member and a slide body mounted on the case body. The actuator body has two arm sections and a notch section positioned between the two arm sections. An operation member and an elastic member are disposed in the notch section. The elastic member serves to make the operation member reciprocally move in an axial direction of the actuator body. The linking member has a first end pivotally connected with the actuator body (or the operation member) and a second end connected with the slide body. When an operator pulls (and pushes) the operation member to move, the actuator body is permitted to move from a closed position to an open position to drive the linking member and the slide body to move.

Abstract: A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.

Abstract: A stitching method for an exposure process includes following steps. A wafer is provided. The wafer includes interposer regions, each of which includes a logic chip region, a first memory chip region, and a second memory chip region. The logic chip region is located between the first and second memory chip regions. A photoresist layer is formed on the wafer. First exposure processes are performed on the photoresist layer by applying a first photomask to form first shot regions in the photoresist layer. Second exposure processes are performed on the photoresist layer by applying a second photomask to form second shot regions in the photoresist layer. The first shot regions and the second shot regions are arranged alternately in a first direction. The first shot regions and the second shot regions are overlapped to form stitching regions, each of which is not located in the logic chip region.

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

Abstract: A backlight module includes a light source, a first prism sheet disposed on the light source, and a light type adjustment sheet disposed on a side of the first prism sheet away from the light source and including a base and multiple light type adjustment structures. The multiple light type adjustment structures are disposed on the first surface of the base. Each light type adjustment structure has a first structure surface and a second structure surface connected to each other. The first structure surface of each light type adjustment structure and the first surface of the base form a first base angle therebetween, and the second structure surface of each light type adjustment structure and the first surface of the base form a second base angle therebetween. The angle of the first base angle is different from the angle of the second base angle.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first semiconductor layer overlying a substrate. A first barrier layer is disposed on the first semiconductor layer. A second semiconductor layer overlies and directly contacts the first barrier layer. A second barrier layer directly contacts the first barrier layer. A third semiconductor layer overlies the second barrier layer. A fourth semiconductor layer overlies the third semiconductor layer. Outer sidewalls of the third semiconductor layer, outer sidewalls of the fourth semiconductor layer, and outer sidewalls of the second barrier layer are respectively aligned.

Abstract: A calibration system and a calibration method for state of charge (SOC) and state of health (SOH) in an energy storage system are provided. The calibration system includes a Main Battery Management System (MBMS) and a plurality of racks, wherein, when the MBMS determines that one of the plurality of racks meets auto-calibration conditions, the MBMS utilizes a battery feature value extraction algorithm to obtain feature value data of each of battery packs, and predicts the number of battery cycles for each of the battery packs via a battery aging correction model. In this way, the SOC and the SOH for each of the battery packs can be accurately calculated, so that maintenance personnel can clearly comprehend the status of each of the racks, thereby improving the efficiency of power management.

Abstract: A semiconductor manufacturing system includes: a nozzle including a first channel that allows a fluid to flow through; a light source configured to emit light; and a light sensor configured to receive light, the light source and the light sensor being disposed within the first channel and opposite to each other. The semiconductor manufacturing system is configured to: emit light, by the light source, from within the nozzle toward a surface while the nozzle is dispensing the fluid; receive the light reflected from the surface by the light sensor, the emitted light and the reflected light adapted to be contained within the fluid; and examine a status of the reflected light. The emitted light and the reflected light propagate in a direction parallel to a longitudinal axis of the first channel.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.

Abstract: An electronic device is disclosed. The electronic device includes a first electronic component and a first interposer. The first electronic component is disposed under the interposer and includes a logic circuit and a power delivery circuit disposed between the interposer and the logic circuit. The interposer and the power delivery circuit are collectively configured to function as a power delivery structure which is electrically connected to the logic circuit.

Abstract: The present disclosure provides a smart pole charging system and a monitoring method. The database system initiates a configuration according to an original environmental status. The charging module is connected with an electric vehicle and provides the electrical energy to the electric vehicle. The monitoring module monitors a real-time environmental status around corresponding smart pole. The calculating module recognizes the real-time environmental status and outputs a calculation result. The router receives the calculation result. The cloud platform is communicated with the router and the database system. The router transmits the calculation result to the cloud platform through an open charge point protocol.

Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.

Abstract: A method includes: positioning a wafer on an electrostatic chuck of a physical vapor deposition apparatus, the wafer including an opening exposing a conductive feature; setting a temperature of the wafer to a room temperature; forming a tungsten thin film in the opening by the physical vapor deposition apparatus, the tungsten thin film including a bottom portion that is on an upper surface of the conductive feature exposed by the opening, a top portion that is on an upper surface of a dielectric layer through which the opening extends and a sidewall portion that is on a sidewall of the dielectric layer exposed by the opening; removing the top portion and the sidewall portion of the tungsten thin film from over the opening; and forming a tungsten plug in the opening on the bottom portion by selectively depositing tungsten by a chemical vapor deposition operation.

Abstract: An optical lens assembly includes, from an object side to an image side, at least four optical lens elements. At least one of the at least four optical lens elements includes an anti-reflective coating. The at least one optical lens element including the anti-reflective coating is made of a plastic material. The anti-reflective coating is arranged on an object-side surface or an image-side surface of the at least one optical lens element including the anti-reflective coating. The anti-reflective coating includes at least one coating layer. One of the at least one coating layer at the outer of the anti-reflective coating is made of ceramics. The anti-reflective coating includes a plurality of holes, and sizes of the plurality of holes adjacent to the outer of the anti-reflective coating are larger than sizes of the plurality of holes adjacent to the inner of the anti-reflective coating.

Abstract: An optical lens assembly includes, from an object side to an image side, at least four optical lens elements. At least one of the at least four optical lens elements includes an anti-reflective coating. The at least one optical lens element including the anti-reflective coating is made of a plastic material. The anti-reflective coating is arranged on an object-side surface or an image-side surface of the at least one optical lens element including the anti-reflective coating. The anti-reflective coating includes at least one coating layer. One of the at least one coating layer at the outer of the anti-reflective coating is made of ceramics. The anti-reflective coating includes a plurality of holes, and sizes of the plurality of holes adjacent to the outer of the anti-reflective coating are larger than sizes of the plurality of holes adjacent to the inner of the anti-reflective coating.