Chun-Wei Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: A bus system is provided. The bus system includes a master device, an enhanced serial peripheral interface (eSPI) bus, a plurality of slave devices electrically connected to the master device via the eSPI bus, and a first resistor. Each slave device has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert handshake control line. The first resistor is coupled between the alert handshake control line and a power supply. Each slave device obtains the number of slave devices according to a first voltage of the alert handshake control line.
Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a semiconductor substrate and a gate structure formed over the fin structure. The semiconductor device structure also includes an isolation feature over a semiconductor substrate and below the gate structure. The semiconductor device structure further includes two spacer elements respectively formed over a first sidewall and a second sidewall of the gate structure. The first sidewall is opposite to the second sidewall and the two spacer elements have hydrophobic surfaces respectively facing the first sidewall and the second sidewall. The gate structure includes a gate dielectric layer and a gate electrode layer separating the gate dielectric layer from the hydrophobic surfaces of the two spacer elements.
Abstract: A high resistance virtual anode for an electroplating cell includes a first layer and a second layer. The first layer includes a plurality of first holes through the first layer. The second layer is over the first layer and includes a plurality of second holes through the second layer.
Abstract: A display panel includes multiple data lines, a scan lines, pixel circuit and a driving circuit. The data lines are configured to receive multiple data signals in a display period. There is a buffer period before the display period. The scan line is configured to receive a scan signal during the display period. The pixel circuit is electrically connected to the data lines and the scan line for receiving the data signals and the scan signal. The driving circuit is electrically connected to the data line, and configured to receive multiple charging signals during the buffer period. The charging signals are corresponding to the data lines and gradually increase so that the driving circuit charges the data lines according to the charging signals.
Abstract: A light-emitting device including at least one light-emitting unit, a wavelength conversion adhesive layer, and a reflective protecting element is provided. The light-emitting unit has an upper surface and a lower surface opposite to each other. The light-emitting unit includes two electrode pads, and the two electrode pads are located on the lower surface. The wavelength conversion adhesive layer is disposed on the upper surface. The wavelength conversion adhesive layer includes a low-concentration fluorescent layer and a high-concentration fluorescent layer. The high-concentration fluorescent layer is located between the low-concentration fluorescent layer and the light-emitting unit. The width of the high-concentration fluorescent layer is WH. The width of the low-concentration fluorescent layer is WL. The width of the light-emitting unit is WE. The light-emitting device further satisfies the following inequalities: WE<WL, WH<WL and 0.8<WH/WE?1.2.
Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.
May 22, 2018
Date of Patent:
October 13, 2020
UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
Abstract: A method includes depositing a contact etch stop layer (CESL) over a gate, a source/drain (S/D) region and an isolation feature. The method includes performing a first chemical mechanical planarization (CMP) to expose the gate. The method further includes performing a second CMP using a slurry different from the first CMP to expose the CESL over the S/D region, wherein, following the second CMP, an entire top surface of the CESL over the S/D region and over the isolation feature is substantially level with a top surface of the gate.
Abstract: In some embodiments, a pixel sensor is provided. The pixel sensor includes a first photodetector arranged in a semiconductor substrate. A second photodetector is arranged in the semiconductor substrate, where a first substantially straight line axis intersects a center point of the first photodetector and a center point of the second photodetector. A floating diffusion node is arranged in the semiconductor substrate at a point that is a substantially equal distance from the first photodetector and the second photodetector. A pick-up well contact region is arranged in the semiconductor substrate, where a second substantially straight line axis that is substantially perpendicular to the first substantially straight line axis intersects a center point of the floating diffusion node and a center point of the pick-up well contact region.
Abstract: A method and an apparatus for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, are provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.
Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.
May 6, 2020
September 24, 2020
Cypress Semiconductor Corporation
Chun Chen, Kuo Tung Chang, Yoram Betser, Shivananda Shetty, Giovanni Mazzeo, Tio Wei Neo, Pawan Singh
Abstract: A touch display panel includes a pixel array, a touch module, and a multiplexer circuit. The pixel array includes a plurality of pixels, a plurality of gate lines, and a plurality of source lines. The pixels are electrically coupled to the source lines and the gate lines. The touch module and the pixel array are overlapped. The multiplexer circuit is coupled between all of the source lines and a source driver and has a plurality of multiplexers. The multiplexers are respectively coupled to n source lines and respectively include a plurality of switches and a bypass trace. The switches are respectively coupled between the first source line to the (n?1)th source line of the n source lines and the source drivers. The bypass trace is coupled between the nth source line of the n source lines and the source driver.
March 11, 2019
Date of Patent:
September 22, 2020
Au Optronics Corporation
Rong-Fu Lin, Chun-Wei Chang, Shu-Hao Huang, Sung-Yu Su, Jie-Chuan Huang, Yun-I Liu
Abstract: A method for manufacturing a golf club head includes aging heat treat a sheet material made of a titanium alloy at 650-750° C. for 10-12 hours to obtain an aging heat treated sheet material. The aging heat treated sheet material is hot rolled to form a striking plate. The striking plate is annealed at 700-800° C. for 30-60 minutes to obtain an annealed striking plate. The annealed striking plate is welded to a club head body made of the titanium alloy to form a semi product. The semi product of the golf head is annealed at 500-700° C. for 30-240 minutes to obtain the golf club head. Thus, the golf club head with a Young's modulus higher than 119 GPa can be manufactured.
Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.
June 8, 2018
Date of Patent:
September 15, 2020
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Abstract: A pixel structure including a substrate, a signal line, a plurality of pixel units and a light blocking pattern layer is provided. The signal line is disposed on the substrate and has opposing first and second sides. Two adjacent pixel units are disposed respectively on the first side and the second side of the signal line. Each pixel units includes an active device, a common electrode, an insulating layer, and a pixel electrode. The insulating layer is located on the common electrode. The pixel electrode is located on the insulating layer and is electrically connected to the active device. The pixel electrode includes an edge strip electrode and a plurality of extension electrodes. The extension electrodes respectively extend from the edge strip electrode toward the signal line. The light blocking pattern layer is located between two adjacent pixel units, and the light blocking pattern layer and the signal line overlap with each other.
Abstract: A driving circuit, a display apparatus and a driving method thereof are provided. The display panel is divided into a plurality of regions including a first region having a rectangular form and a second region having a free form. The driving circuit generates a plurality of control clocks having a first duty cycle during a first period and a second duty cycle different from the first duty cycle during a second period, or having a first phase shift during the first period and a second phase shift different from the first phase shift during the second period, or having a first driving capability during the first period and a second driving capability different from the first driving capability during the second period.
Abstract: A display has rows and columns of pixels (22). A data line (Dn) in each column provides image data signals to the pixels of that column. Each row has first and second control lines (select[m], monitor[m]) coupled to the gates of first and second respective transistors (SE, MO) in each pixel. A third transistor in each pixel serves as a drive transistor (DR) and is coupled in series with a light-emitting diode (30) between positive and ground power supply voltages (VDD, VSS). A display driver circuitry in the display characterizes each of the light-emitting diodes in a column using the data line in an adjacent column from that light-emitting diode. Each of the drive transistors in a column is characterized using the data line in that column and the data line in an adjacent column.
Abstract: In a method of manufacturing a photo mask, a resist layer is formed over a mask blank, which includes a mask substrate, a phase shift layer disposed on the mask substrate and a light blocking layer disposed on the phase shift layer. A resist pattern is formed by using a lithographic operation. The light blocking layer is patterned by using the resist pattern as an etching mask. The phase shift layer is patterned by using the patterned light blocking layer as an etching mask. A border region of the mask substrate is covered with an etching hard cover, while a pattern region of the mask substrate is opened. The patterned light blocking layer in the pattern region is patterned through the opening of the etching hard cover. A photo-etching operation is performed on the pattern region to remove residues of the light blocking layer.
Abstract: A memory access interface device that includes a clock generation circuit that generates reference clock signals according to a source clock signal and access signal transmission circuits are provided. Each of the access signal transmission circuits includes a first and a second clock frequency division circuits, a phase adjusting circuit and a duty cycle adjusting circuit. The first and the second clock frequency division circuits sequentially divide the frequency of one of the reference clock signals to generate a first and a second frequency divided clock signals respectively. The phase adjusting circuit adjusts the phase of an access signal according to the second frequency divided clock signal to generate a phase-adjusted access signal. The duty cycle adjusting circuit adjusts the duty cycle of the phase-adjusted access signal to be a half of the time period to generate an output access signal to access a memory device.
Abstract: The present invention provides a radioactive labeling method for neuropeptide Y (NPY) compound and a mammalian diagnostic radioactive targeting medicine with NPY peptide being modified at position 27th to 36th, and after binding with the chelating agent and labeling the radiation nucleus 66Ga, 67Ga, 68Ga, 177Lu or 111In to provide a radioactive targeting medicine for multi-type breast cancer diagnosis and treatment.