Patents by Inventor Chun-Wei Chang

Chun-Wei Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250102580
    Abstract: A calibration system and a calibration method for state of charge (SOC) and state of health (SOH) in an energy storage system are provided. The calibration system includes a Main Battery Management System (MBMS) and a plurality of racks, wherein, when the MBMS determines that one of the plurality of racks meets auto-calibration conditions, the MBMS utilizes a battery feature value extraction algorithm to obtain feature value data of each of battery packs, and predicts the number of battery cycles for each of the battery packs via a battery aging correction model. In this way, the SOC and the SOH for each of the battery packs can be accurately calculated, so that maintenance personnel can clearly comprehend the status of each of the racks, thereby improving the efficiency of power management.
    Type: Application
    Filed: January 22, 2024
    Publication date: March 27, 2025
    Applicant: SIMPLO TECHNOLOGY CO., LTD.
    Inventors: Ya-Mei CHANG, Chi-Yang CHENG, Chun-Chang CHEN, Chia-Wei CHEN
  • Publication number: 20250096022
    Abstract: A semiconductor manufacturing system includes: a nozzle including a first channel that allows a fluid to flow through; a light source configured to emit light; and a light sensor configured to receive light, the light source and the light sensor being disposed within the first channel and opposite to each other. The semiconductor manufacturing system is configured to: emit light, by the light source, from within the nozzle toward a surface while the nozzle is dispensing the fluid; receive the light reflected from the surface by the light sensor, the emitted light and the reflected light adapted to be contained within the fluid; and examine a status of the reflected light. The emitted light and the reflected light propagate in a direction parallel to a longitudinal axis of the first channel.
    Type: Application
    Filed: December 5, 2024
    Publication date: March 20, 2025
    Inventors: KAI-LIN CHUANG, TSUNG-CHI CHEN, PEI-JUNG CHANG, CHUN-WEI HUANG, JUN XIU LIU
  • Patent number: 12249542
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.
    Type: Grant
    Filed: November 17, 2023
    Date of Patent: March 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hao Kung, Chih-Chieh Chang, Kao-Feng Liao, Hui-Chi Huang, Kei-Wei Chen
  • Publication number: 20250081730
    Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.
    Type: Application
    Filed: June 26, 2024
    Publication date: March 6, 2025
    Inventors: Andrew Lin, Alper Ozgurluk, Chao Liang Chien, Cheuk Chi Lo, Chia-Yu Chen, Chien-Chung Wang, Chih Pang Chang, Chih-Hung Yu, Chih-Wei Chang, Chin Wei Hsu, ChinWei Hu, Chun-Kai Tzeng, Chun-Ming Tang, Chun-Yao Huang, Hung-Che Ting, Jung Yen Huang, Lungpao Hsin, Shih Chang Chang, Tien-Pei Chou, Wen Sheng Lo, Yu-Wen Liu, Yung Da Lai
  • Publication number: 20250074247
    Abstract: The present disclosure provides a smart pole charging system and a monitoring method. The database system initiates a configuration according to an original environmental status. The charging module is connected with an electric vehicle and provides the electrical energy to the electric vehicle. The monitoring module monitors a real-time environmental status around corresponding smart pole. The calculating module recognizes the real-time environmental status and outputs a calculation result. The router receives the calculation result. The cloud platform is communicated with the router and the database system. The router transmits the calculation result to the cloud platform through an open charge point protocol.
    Type: Application
    Filed: October 18, 2023
    Publication date: March 6, 2025
    Inventors: Ting-Chi Chang, Chun-Ta Chen, Che-Hsien Lien, Yu-Cheng Lee, Tien-Chun Wang, Chun-Wei Hu
  • Publication number: 20250079308
    Abstract: An electronic device is disclosed. The electronic device includes a first electronic component and a first interposer. The first electronic component is disposed under the interposer and includes a logic circuit and a power delivery circuit disposed between the interposer and the logic circuit. The interposer and the power delivery circuit are collectively configured to function as a power delivery structure which is electrically connected to the logic circuit.
    Type: Application
    Filed: August 29, 2023
    Publication date: March 6, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hao-Chih HSIEH, Chun-Kai CHANG, Chao Wei LIU
  • Publication number: 20250066899
    Abstract: A method includes: positioning a wafer on an electrostatic chuck of a physical vapor deposition apparatus, the wafer including an opening exposing a conductive feature; setting a temperature of the wafer to a room temperature; forming a tungsten thin film in the opening by the physical vapor deposition apparatus, the tungsten thin film including a bottom portion that is on an upper surface of the conductive feature exposed by the opening, a top portion that is on an upper surface of a dielectric layer through which the opening extends and a sidewall portion that is on a sidewall of the dielectric layer exposed by the opening; removing the top portion and the sidewall portion of the tungsten thin film from over the opening; and forming a tungsten plug in the opening on the bottom portion by selectively depositing tungsten by a chemical vapor deposition operation.
    Type: Application
    Filed: August 23, 2023
    Publication date: February 27, 2025
    Inventors: Chun-Yen LIAO, I. LEE, Shu-Lan CHANG, Sheng-Hsuan LIN, Feng-Yu CHANG, Wei-Jung LIN, Chun-I TSAI, Chih-Chien CHI, Ming-Hsing TSAI, Pei Shan CHANG, Chih-Wei CHANG
  • Patent number: 12235409
    Abstract: An optical lens assembly includes, from an object side to an image side, at least four optical lens elements. At least one of the at least four optical lens elements includes an anti-reflective coating. The at least one optical lens element including the anti-reflective coating is made of a plastic material. The anti-reflective coating is arranged on an object-side surface or an image-side surface of the at least one optical lens element including the anti-reflective coating. The anti-reflective coating includes at least one coating layer. One of the at least one coating layer at the outer of the anti-reflective coating is made of ceramics. The anti-reflective coating includes a plurality of holes, and sizes of the plurality of holes adjacent to the outer of the anti-reflective coating are larger than sizes of the plurality of holes adjacent to the inner of the anti-reflective coating.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: February 25, 2025
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Wen-Yu Tsai, Chien-Pang Chang, Chi-Wei Chi, Wei-Fong Hong, Chun-Hung Teng, Kuo-Chiang Chu
  • Patent number: 12235410
    Abstract: An optical lens assembly includes, from an object side to an image side, at least four optical lens elements. At least one of the at least four optical lens elements includes an anti-reflective coating. The at least one optical lens element including the anti-reflective coating is made of a plastic material. The anti-reflective coating is arranged on an object-side surface or an image-side surface of the at least one optical lens element including the anti-reflective coating. The anti-reflective coating includes at least one coating layer. One of the at least one coating layer at the outer of the anti-reflective coating is made of ceramics. The anti-reflective coating includes a plurality of holes, and sizes of the plurality of holes adjacent to the outer of the anti-reflective coating are larger than sizes of the plurality of holes adjacent to the inner of the anti-reflective coating.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: February 25, 2025
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Wen-Yu Tsai, Chien-Pang Chang, Chi-Wei Chi, Wei-Fong Hong, Chun-Hung Teng, Kuo-Chiang Chu
  • Patent number: 12219123
    Abstract: A method for rendering data of a three-dimensional image adapted to an eye position and a display system are provided. The method is used to render the three-dimensional image to be displayed in a three-dimensional space. In the method, a three-dimensional image data used to describe the three-dimensional image is obtained. The eye position of a user is detected. The ray-tracing information between the eye position and each lens unit of a multi-optical element module forms a region of visibility (RoV) that may cover a portion of the three-dimensional image in the three-dimensional space. When coordinating the physical characteristics of a display panel and the multi-optical element module, a plurality of elemental images can be obtained. The elemental images form an integral image that records the three-dimensional image data adapted to the eye position, and the integral image is used to reconstruct the three-dimensional image.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: February 4, 2025
    Assignee: LIXEL INC.
    Inventors: Chun-Hsiang Yang, Chih-Hung Ting, Kai-Chieh Chang, Hsin-You Hou, Chih-Wei Shih, Wei-An Chen, Kuan-Yu Chen
  • Publication number: 20250019684
    Abstract: A method for maintaining lamellar structure of cell, configured to manufacture a lamellar cell product, comprises the following steps of: seeding a predetermined number of cells in a culture device containing a first culture medium and culturing the predetermined number of cells for a predetermined time to form a cell planar structure; placing a mold in the culture device to cover at least an outer portion of the cell planar structure; adding a gel into the culture device with the mold to envelop the cell planar structure; and separating the gel and the cell planar structure enveloped therein from the culture device and the mold to form the lamellar cell product.
    Type: Application
    Filed: July 5, 2024
    Publication date: January 16, 2025
    Inventors: Hong-Nerng Ho, Heng-Yu Liu, Chen-Wei Lan, Chung-Wei Chang, Bo-He Chen, Chui Wei Wong, Chun-Lin Liu
  • Publication number: 20250015246
    Abstract: A semiconductor device is provided, which includes an active region, a first semiconductor layer, a first metal element-containing structure, a first p-type or n-type layer, a second semiconductor layer and an insulating layer. The active region has a first surface and a second surface. The first semiconductor layer is at the first surface. The first metal element-containing structure covers the first semiconductor layer and comprising a first metal element. The first p-type or n-type layer is between the first semiconductor layer and the first metal element-containing structure. The second semiconductor layer is between the first semiconductor layer and the first p-type or n-type layer. The insulating layer covers a portion of the first semiconductor layer and a portion of the second semiconductor. The first p-type or n-type layer includes an oxygen element (O) and a second metal element and has a thickness less than or equal to 20 nm.
    Type: Application
    Filed: September 23, 2024
    Publication date: January 9, 2025
    Inventors: Yu-Tsu LEE, Yi-Yang CHIU, Chun-Wei CHANG, Min-Hao YANG, Wei-Jen HSUEH, Yi-Ming CHEN, Shih-Chang LEE, Chung-Hao WANG
  • Publication number: 20240421537
    Abstract: The present invention relates to a lockable connector assembly, including a wire-end connector and a board-end connector. The wire-end connector includes a first body and a locking member. The first body has a flexible positioning member and a side guide groove. The locking member is movably disposed in the side guide groove. When the locking member is located in an initial position, the wire-end connector is capable of being engaged with the board-end connector. When the locking member is moved from the initial position to an insertion position, the locking member is abutted against the flexible positioning member so that the flexible positioning member is fixedly disposed in the locked position.
    Type: Application
    Filed: January 17, 2024
    Publication date: December 19, 2024
    Inventors: Hsien-Chang LIN, Chun-Wei CHANG
  • Publication number: 20240407658
    Abstract: A method for obtaining a heart rate value by an optical sensing apparatus includes: receiving, by a first calculator in a processor and from a light receiver, a PPG signal; receiving, by a second calculator in the processor and from a motion sensor, a motion signal; determining, by the first calculator, a first heart rate value; determining, by the first calculator, a validity indicator according to the PPG signal; and determining, by the second calculator, a second heart rate value according to the PPG signal and the motion signal. When the validity indicator is determined to satisfy a predetermined requirement, the processor outputs the first heart rate value as the heart rate value. When the validity indicator is determined to not satisfy the predetermined requirement, the processor outputs the second heart rate value as the heart rate value.
    Type: Application
    Filed: June 14, 2024
    Publication date: December 12, 2024
    Inventors: Jui-Wei Tsai, Chun-Wei Chang, Chieh Yin, Kai-Wei Chiu
  • Publication number: 20240413268
    Abstract: A semiconductor device includes a semiconductor stack, a reflective structure, and a conductive structure. The semiconductor stack includes a first semiconductor structure, a second semiconductor structure and an active region located between the first semiconductor structure and the second semiconductor structure. The reflective structure is located at a side of semiconductor stack closed to the first semiconductor structure, and includes a first metal. The conductive structure locates between the reflective structure and the first semiconductor structure, and includes a first region overlapping with the active structure and a second region which does not overlap with the active structure. The first metal in the second region has a concentration smaller than 5 atomic percent.
    Type: Application
    Filed: June 7, 2024
    Publication date: December 12, 2024
    Inventors: Yi-Yang CHIU, Chun-Yu LIN, Chun Wei CHANG, Yi-Ming CHEN, Chen OU, Hung-Yu CHOU, Liang-Yi WU, Hsiao-Chi YANG
  • Publication number: 20240413069
    Abstract: A semiconductor structure includes a substrate, a through via penetrating the substrate, a trench capacitor, a first RDL, a second RDL, a contact feature, and a chip. The trench capacitor extends from a back surface toward a front surface of the substrate, wherein the trench capacitor is separated from an active area at the front surface of the substrate. The first RDL is disposed over the front surface and electrically connecting to the through via. The second RDL is disposed over the back surface of the substrate and electrically connecting to the through via and the trench capacitor. The contact feature is disposed over the second RDL and electrically connecting to the trench capacitor through the second RDL. The chip is bonded over the front surface of the substrate. A method of manufacturing the semiconductor structure is also provided.
    Type: Application
    Filed: June 4, 2024
    Publication date: December 12, 2024
    Inventors: TZU-WEI CHIU, CHUN-WEI CHANG, WEI-CHIH CHEN, CHE-YEN HUANG
  • Publication number: 20240394462
    Abstract: An electromigration (EM) sign-off methodology that utilizes a system for analyzing an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes a memory and a processor configured for calculating adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat dissipating elements located within a defined thermal coupling volume or range of the heat sensitive structures.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Hsien Yu TSENG, Amit KUNDU, Chun-Wei CHANG, Szu-Lin LIU, Sheng-Feng LIU
  • Patent number: D1062545
    Type: Grant
    Filed: May 7, 2023
    Date of Patent: February 18, 2025
    Assignees: Acer Incorporated, Acer Gadget Inc.
    Inventors: Yun Cheng, Ker-Wei Lin, Hao-Ming Chang, Chun-Ta Chen, Wei-Chen Lee, Chih-Yuan Chang
  • Patent number: D1063712
    Type: Grant
    Filed: May 7, 2023
    Date of Patent: February 25, 2025
    Assignees: Acer Incorporated, Acer Gadget Inc.
    Inventors: Yun Cheng, Ker-Wei Lin, Hao-Ming Chang, Chun-Ta Chen, Wei-Chen Lee, Chih-Yuan Chang
  • Patent number: D1067795
    Type: Grant
    Filed: March 20, 2023
    Date of Patent: March 25, 2025
    Assignee: HONG-MING TECHNOLOGY CO., LTD.
    Inventor: Chun Wei Chang