Abstract: A dual image capture assembly for acquiring and transmitting images from a binocular scope for three-dimensional (3D) viewing on a user computing device. The dual image capture assembly includes a pair of eyepiece adaptors each configured to attach on the pair of eyepieces of a binocular scope, and a dual-camera apparatus including a pair of image capture devices respectively coupled with the pair of eyepiece adaptors. The dual-camera apparatus also includes a linker connecting the first and second camera components.

Abstract: The present disclosure provides a video encoding circuit and a wireless video transmission apparatus and method. The wireless video transmission apparatus includes a wireless transmitter circuit and a video encoding circuit. The wireless transmitter circuit is configured to transmit a video stream with a bit rate to a wireless transmission channel and provide a transmission state message according to a transmission state of the wireless transmission channel. The video encoding circuit is coupled to the wireless transmitter circuit to receive the transmission state message. The video encoding circuit is configured to perform an encoding operation on video data to generate the video stream to the wireless transmitter circuit and dynamically adjust the bit rate of the video stream delivered to the wireless transmitter circuit according to the transmission state message.

Abstract: A touch display panel and controlling method thereof are provided. The touch display panel includes a first substrate, a second substrate, a display medium layer, a first common electrode, and a pixel structure including a pixel electrode and a second common electrode. The first common electrode has a voltage signal. In a display mode, the pixel electrode is provided with a data signal so that a first voltage difference exists between the first and the second common electrodes. The arrangement of the display medium layer varies according to the data signal and the first voltage difference. In a touch mode, the second common electrode is provided with an indication signal whose waveform alternates between first and second voltage values. When the indication signal is at the first voltage value and a second voltage value respectively, a second and a third voltage differences exist between the first and second common electrodes.

Abstract: A securing assembly which can present and secure a tablet computer for example in a door of a refrigerator includes a receiving space for securing a display of the computer. At least one limiting opening and at least one slot are defined in one of the securing assembly or the display, the other one comprises at least one limiting post and at least one latch. The at least one limiting post is latched to the at least one limiting opening, the at least one latch is latched to the at least one slot, thereby securing the display to the securing assembly in a first direction. A refrigerator employing the securing assembly is also provided.

Abstract: A touch display device includes a plurality of scan lines including first portion scan lines and second portion scan lines; a plurality of data lines crossing the plurality of scan lines; a scan driver outputs a plurality of first portion scan signals to the first portion scan lines in a first display scan period in a frame, a plurality of second portion scan signals to the second portion scan lines in a second display scan period in the frame; and a data driver outputs a plurality of first portion display signals corresponding to the plurality of first portion scan signals in the first display scan period; a plurality of second portion display signals corresponding to the plurality of second portion scan signals in the second display scan period.

Abstract: A control circuit disposed in a connection line including a first power pin and a second power pin and including a native N-type transistor, a first impedance unit, and a second impedance unit is provided. The native N-type transistor includes a first gate, a first drain and a first source. The first drain is coupled to the first power pin. The first impedance unit is coupled between the first source and the second power pin. The second impedance unit is coupled between the first drain and the first gate. When the voltage level of the first power pin is equal to a pre-determined level, the first gate of the native N-type transistor receives an adjusting signal to adjust an equivalent impedance of the native N-type transistor.

Abstract: A foldable display device includes a holding structure and a flexible display panel. The holding structure includes a soft outer housing, a first inner housing, a second inner housing, a first supporting stage, a second supporting stage, a first hinge, a first spring element, a second hinge, and a second spring element. The first hinge is connected to a same side of the first inner housing and the first supporting stage. The first spring element is connected to another same side of the first inner housing and the first supporting stage. The second hinge is connected to a same side of the second inner housing and the second supporting stage. The second spring element is connected to another same side of the second inner housing and the second supporting stage. The flexible display panel is located on the first and second supporting stages.

Abstract: A foldable display device includes a display panel having two flat portions and a bend portion between the two flat portions; a hinge substantially aligned with and beneath the bend portion of the display panel; a plurality of slidable platforms between the hinge and a bottom surface of the bend portion of the display panel; and a repeatable adhering component between one of the slidable platforms and the bottom surface of the bend portion of the display panel, wherein the repeatable adhering component comprises a self-adhesive pad or a weak adhesive.

Abstract: A drill bit includes a cutting head and a bit body. The cutting head has a tip and cutting parts. The bit body is connected to the cutting head and has a longitudinal axis extending through the tip. The bit body has chip discharge flutes. The cutting parts are disposed at different angular positions around the longitudinal axis. Each cutting part is concaved inwardly and bounds one of the chip discharge flutes. Each of the cutting parts includes a rake face that has a corner edge adjacent to a respective one of the chip discharge flutes. When a bottom of the cutting head is viewed in a direction parallel to the longitudinal axis of the bit body, the corner edge has an obtuse included angle.

Abstract: A bufferable femoral implant includes a metallic main body, and an elastomer member integrally formed or connected to a lower portion of the metallic main body, whereby when an external force acts upon the femoral implant as implanted in a patient's femur, the elastomer member as packed within the medullary cavity in the femur will bufferably dampen such an external force for safely protecting the patient's femur, the femoral implant and the related hip bones.

Abstract: A circuit structure includes a flexible substrate, an inorganic barrier layer, a first wire, a second wire, a third wire, a fourth wire, an organic dielectric layer, a first conductive via, and a second conductive via. The inorganic barrier layer is disposed over the flexible substrate. The first and second wires are disposed on the inorganic barrier layer and contact the inorganic barrier layer. The first and second wires are separated from each other. The organic dielectric layer is disposed over the first and second wires. The third wire is disposed in the organic dielectric layer. The fourth wire is disposed above the organic dielectric layer. The first conductive via is disposed in the organic dielectric layer and contacts the first and third wires. The second conductive via is disposed in the organic dielectric layer and contacts the second and fourth wires.

Abstract: A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate.

Abstract: A flexible laminated structure includes a first protection layer, a second protection layer directly contacting the first protection layer and a flexible material layer. The second protection layer having a plurality of openings, which are used to expose a portion of the first protection layer. The flexible material layer is disposed on the second protection layer and extends into the openings, and directly contacts the first protection layer exposed by the openings. An adhesion between the flexible material layer and the first protection layer is greater than an adhesion between the second protection layer and the first protection layer.

Abstract: A flexible laminated structure includes a first protective layer, a plurality of patterned structures, and a second protective layer. The patterned structures are disposed on the first protective layer and expose a portion of the first protective layer. Each of the patterned structures has a first width adjacent to the first protective layer and a second width away from the first protective layer, and the first width is smaller than the second width. The second protective layer is disposed on the first protective layer and covers the patterned structures and the first protective layer.

Abstract: A carrier apparatus is adapted to carry a flexible substrate. The carrier apparatus includes two carrier plates, two adhesive layers, and two supporting units. The carrier plates have a gap with respect to each other, and each of the carrier plates has a first region and a second region, wherein the second regions of the carrier plates are adjacent to each other and are located between the first regions. The adhesive layers are respectively disposed in the first regions of the carrier plates. The supporting units are respectively disposed in the second regions of the carrier plates and are coplanar with the adhesive layers, wherein the flexible substrate is fixed on the carrier plates through the adhesive layers, and the supporting units are detachably attached to a bending zone of the flexible substrate by attractive force. A display including the carrier apparatus and a flexible display panel is provided.

Abstract: An in-cell touch display device includes an in-cell touch panel, a backlight module driving circuit, a backlight module, a gate driving circuit, a touch processing circuit and a control circuit. The in-cell touch panel includes a plurality of gate lines and a plurality of touch sensing units. The control circuit is used for defining a plurality of gate line driving periods separated from each other in the time and at least one touch sensing period in a frame period. The touch sensing period is between two adjacent gate line driving periods. During the gate line driving periods, the control circuit controls the gate driving circuit to drive the gate lines sequentially and outputs a signal to the backlight module driving circuit to turn on the backlight module. During each touch sensing period, the control circuit controls the touch processing circuit to output a driving signal to the touch sensing units and outputs a signal to the backlight module driving circuit to turn off the backlight module.

Abstract: A gate line drive circuit includes first, second and third transistors, and a boosting capacitor. The first transistor has a control terminal connected to a charge/discharge control signal of a previous-stage gate line drive circuit, a first terminal, and a second terminal connected to a control node. The second transistor has a control terminal connected to the control node, a first terminal, and a second terminal connected to a first timing signal. The third transistor has a control terminal connected to the control node, a first terminal, and a second terminal connected to a second timing signal. The boosting capacitor has one terminal connected to the control node, and the other terminal connected to the first terminal of the third transistor and a control terminal of a first transistor of a next-stage gate line drive circuit. The first terminal of the second transistor is connected to a gate line.

Abstract: A method and a system for recommending an application parameter setting and a system specification setting in a distributed computation are provided. The method includes the following steps. An application information, a framework information and a system information are received. Whether a performance model which includes a relationship of a performance, the application information, the framework information and the system information is stored in a storage unit is determined. The application parameter setting and the system specification setting are obtained according to the performance model, if the performance model is stored in the storage unit.

Abstract: A gate line drive circuit includes first, second and third transistors, and a boosting capacitor. The first transistor has a control terminal connected to a charge/discharge control signal of a previous-stage gate line drive circuit, a first terminal, and a second terminal connected to a control node. The second transistor has a control terminal connected to the control node, a first terminal, and a second terminal connected to a first timing signal. The third transistor has a control terminal connected to the control node, a first terminal, and a second terminal connected to a second timing signal. The boosting capacitor has one terminal connected to the control node, and the other terminal connected to the first terminal of the third transistor and a control terminal of a first transistor of a next-stage gate line drive circuit. The first terminal of the second transistor is connected to a gate line.