Patents by Inventor Chun Yeh

Chun Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170049477
    Abstract: An apparatus, adapted for resiliently holding resected fibula sections, comprises: a first connecting portion adapted for connecting a first resected fibular section of a patient's fibula; a second connecting portion adapted for connecting a second resected fibular section of the patient's fibula; and an elastic portion or member defined between the first connecting portion and the second connecting portion adapted for resiliently holding the first resected fibular section and the second resected fibular section, whereby upon actuation by an impacting force caused by the patient's movement, the elastic portion may resiliently buffer such an impacting force to prevent contacting or rejoining of the first and second resected fibular sections.
    Type: Application
    Filed: July 21, 2016
    Publication date: February 23, 2017
    Inventor: Chung-Chun Yeh
  • Patent number: 9577091
    Abstract: A vertical transistor and a manufacturing method thereof are provided herein. The manufacturing method includes forming a first patterned conductive layer on a substrate; forming a patterned metal oxide layer on the first patterned conductive layer, in which the patterned metal oxide layer includes a first patterned insulator layer, a second patterned insulator layer, and a second patterned conductive layer; forming a semiconductor layer; and forming a third patterned conductive layer. The first patterned insulator layer, the second patterned insulator layer, and the second patterned conductive layer are made by using a single metal oxide material. The oxygen concentration of the second patterned conductive layer is different from the oxygen concentrations of the first patterned insulator layer and the second patterned insulator layer.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: February 21, 2017
    Assignee: E Ink Holdings Inc.
    Inventors: Chia-Chun Yeh, Wei-Tsung Chen, Cheng-Hang Hsu, Ted-Hong Shinn
  • Publication number: 20170047494
    Abstract: A light-emitting device, including a substrate; a plurality of light-emitting units formed on the substrate, wherein the plurality of light-emitting units include a first light-emitting unit; a second light-emitting unit; and a group of light-emitting units formed between the first light-emitting unit and the second light-emitting unit, wherein each of the plurality of light-emitting unit includes a first-type semiconductor layer, a second-type semiconductor layer and an active layer formed between the first-type semiconductor layer and the second-type semiconductor layer; a plurality of electrical connections formed on the plurality of light-emitting units, electrically connecting each two of the light-emitting units adjacent; a first pad formed on the first light-emitting unit; a second pad and a third pad formed on the second light-emitting unit; wherein one of the plurality of electrical connection connects and extends from the second pad.
    Type: Application
    Filed: August 13, 2015
    Publication date: February 16, 2017
    Applicant: EPISTAR CORPORATION
    Inventors: Hui-Chun YEH, Chien-Fu SHEN, Tsun-Kai KO
  • Publication number: 20170047908
    Abstract: A control circuit disposed in a connection line including a first power pin and a second power pin and including a native N-type transistor, a first impedance unit, and a second impedance unit is provided. The native N-type transistor includes a first gate, a first drain and a first source. The first drain is coupled to the first power pin. The first impedance unit is coupled between the first source and the second power pin. The second impedance unit is coupled between the first drain and the first gate. When the voltage level of the first power pin is equal to a pre-determined level, the first gate of the native N-type transistor receives an adjusting signal to adjust an equivalent impedance of the native N-type transistor.
    Type: Application
    Filed: December 21, 2015
    Publication date: February 16, 2017
    Inventor: Cheng-Chun Yeh
  • Patent number: 9564537
    Abstract: Disclosed herein is a method for manufacturing an array substrate. The method includes forming a source electrode and a drain electrode on a substrate. A semiconductor layer, an organic insulating layer, and a gate electrode layer are sequentially formed to cover the substrate, the source electrode, and the drain electrode. A patterned photoresist layer is formed on the gate electrode layer. The exposed portion of the gate electrode layer, and a portion of the organic insulative layer and a portion of the semiconductor layer thereunder are removed to form a gate electrode. An organic passivation layer is formed on the gate electrode, the source electrode, and the drain electrode. The organic passivation layer has a contact window to expose a portion of the drain electrode. A pixel electrode is formed on the organic passivation layer and the exposed portion of the drain electrode.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: February 7, 2017
    Assignee: E Ink Holdings Inc.
    Inventors: Wei-Chou Lan, Ted-Hong Shinn, Henry Wang, Chia-Chun Yeh
  • Publication number: 20170012167
    Abstract: A light-emitting device comprises a semiconductor layer sequence comprising a first semiconductor layer having a first electrical conductivity, a second semiconductor layer having a second electrical conductivity, and an active layer interposed between the first semiconductor layer and the second semiconductor layer; a plurality of beveled trenches formed in the semiconductor layer sequence; a plurality of protruding structures respectively formed in the plurality of beveled trenches; a dielectric layer formed on the second semiconductor layer and an inner sidewall of the plurality of beveled trenches; a reflecting layer interposed between the semiconductor layer sequence and the dielectric layer; and a metal layer formed along the inner sidewall of the plurality of beveled trenches, wherein the dielectric layer, the reflecting layer and the metal layer are overlapping, the plurality of protruding structures and the reflecting layer are not overlapping.
    Type: Application
    Filed: September 22, 2016
    Publication date: January 12, 2017
    Inventors: Chao-Hsing CHEN, Yu-Chen YANG, Li-Ping JOU, Hui-Chun YEH, Yi-Wen KU
  • Publication number: 20160377913
    Abstract: An LCD panel includes first and second substrates, signal lines, pixel structures, first, second, and third color filter pattern layers, a light-shielding pattern layer, and a liquid crystal medium. The second substrate has first and second light-shielding regions and first, second and third light-transmissive regions. The first and second light-shielding regions define the first, second and third light-transmissive regions. The first color filter pattern layer is correspondingly located in the first light-transmissive regions and the first light-shielding regions. The second color filter pattern layer is correspondingly located in the second light-transmissive regions and the first light-shielding regions. The first and second color filter pattern layers are stacked together in the first light-shielding regions. The third color filter pattern layer is correspondingly located in the third light-transmissive regions.
    Type: Application
    Filed: December 27, 2015
    Publication date: December 29, 2016
    Inventors: Pi-Chun Yeh, Ching-Sheng Cheng
  • Publication number: 20160372635
    Abstract: An optoelectronic semiconductor device comprises a substrate; a semiconductor system including a first conductivity layer, a second conductivity layer, and a conversion unit between the first conductivity layer and the second conductivity layer, wherein the first conductivity layer is closer to the substrate than the second conductivity layer is to the substrate, and the second conductivity layer comprises a top surface perpendicular to a thickness direction of the semiconductor system, and in a top view of the semiconductor system, an outline of the first conductivity layer surrounds an outline of the second conductivity layer; a first electrical connector on the first conductivity layer of the semiconductor system; a second electrical connector comprising a shape formed on the second conductivity layer of the semiconductor system; and a contact layer formed on the top surface of the second conductivity layer and having an outer perimeter at an inner side of the outline of the second conductivity layer in th
    Type: Application
    Filed: September 2, 2016
    Publication date: December 22, 2016
    Inventors: Tsun-Kai KO, Schang-Jing HON, Chien-Kai CHUNG, Hui-Chun YEH, An-Ju LIN, Chien-Fu SHEN, Chen OU
  • Patent number: 9513670
    Abstract: A touch panel including a substrate, at least one touch-sensing unit, at least one connecting pad, at least a testing line, at least one ESD protection circuit, and a first isolation layer is provided. The touch-sensing unit is disposed on the substrate. The connecting pad is disposed on the substrate and electrically connected to the touch-sensing unit. The testing line is disposed on the substrate, electrically connected to the connecting pad, and extends to at least an edge of the substrate. The ESD protection circuit is disposed in the edge of the substrate and electrically connected to a ground voltage, wherein a vertical projection of the testing line to the substrate and that of the ESD protection circuit to the substrate is at least partially overlapped. The first isolation layer is disposed between the testing line and the ESD protection circuit.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: December 6, 2016
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Yi-Chi Chen, Chia-Chun Yeh, Chien-Yu Chen, Yi-Ling Lin, Yi-Hsin Lin
  • Patent number: 9508902
    Abstract: An optoelectronic semiconductor device in accordance with an embodiment of present invention includes a conversion unit having a first side; an electrical connector; a contact layer having an outer perimeter; and at least three successive discontinuous-regions formed along the outer perimeter and having at least one different factor; wherein the electrical connector, the contact layer, and the discontinuous-regions are formed on the first side of the conversion unit.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: November 29, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Tsun-Kai Ko, Schang-Jing Hon, Chien-Kai Chung, Hui-Chun Yeh, An-Ju Lin, Chien-Fu Shen, Chen Ou
  • Patent number: 9508901
    Abstract: A light-emitting device comprises: a first semiconductor layer; a transparent conductive oxide layer including a diffusion region having a first metal material and a non-diffusion region devoid of the first metal material, wherein the non-diffusion region is closer to the first semiconductor layer than the diffusion region; and a metal layer formed on the transparent conductive oxide layer, wherein the metal layer is pervious to a light emitted from the active layer and comprises a pattern.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: November 29, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Juin-Yang Chen, De-Shan Kuo, Chun-Hsiang Tu, Po-Shun Chiu, Chien-Kai Chung, Hui-Chun Yeh, Min-Yen Tsai, Tsun-Kai Ko, Chun-Teng Ko
  • Publication number: 20160310281
    Abstract: A bufferable femoral implant includes a metallic main body, and an elastomer member integrally formed or connected to a lower portion of the metallic main body, whereby when an external force acts upon the femoral implant as implanted in a patient's femur, the elastomer member as packed within the medullary cavity in the femur will bufferably dampen such an external force for safely protecting the patient's femur, the femoral implant and the related hip bones.
    Type: Application
    Filed: April 15, 2016
    Publication date: October 27, 2016
    Inventor: CHUNG-CHUN YEH
  • Publication number: 20160309621
    Abstract: A rack having a plurality of fans and a plurality of servers divided into several groups is presented. Each of the servers calculates fan speed needed for heat dissipating based on internal temperatures, and outputs the calculated fan speed to the fans in same group respectively. The fans in the same group run according to the received fan speed. A rack management controller (RMC) in the rack obtains the fan speed outputted by a server in one of the several groups, and calculates a fan speed compensating value based on the obtained fan speed. The RMC then outputs the fan speed compensating value to fans in neighboring groups to make it to run according to the fan speed compensating value.
    Type: Application
    Filed: April 16, 2015
    Publication date: October 20, 2016
    Inventors: Yen-Yu CHEN, Wan-Chun YEH, Yu-Heng SU, Shih-Chieh HSU
  • Patent number: 9472725
    Abstract: A light-emitting device comprises a semiconductor layer sequence comprising a first semiconductor layer having a first electrical conductivity, a second semiconductor layer having a second electrical conductivity, and an active layer interposed between the first semiconductor layer and the second semiconductor layer; a plurality of protruding structures; a plurality of beveled trenches in the semiconductor layer sequence and respectively accommodating the plurality of protruding structures; a dielectric layer on the second semiconductor layer and an inner sidewall of the plurality of beveled trenches, wherein the dielectric layer comprises a surface perpendicular to a thickness direction of the semiconductor layer sequence; a metal layer formed along the inner sidewall of the plurality of beveled trenches and extending to the surface of the dielectric layer, wherein the metal layer is insulated from the second semiconductor layer by the dielectric layer; and a first electrode formed on the plurality of protru
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: October 18, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Yu-Chen Yang, Li-Ping Jou, Hui-Chun Yeh, Yi-Wen Ku
  • Patent number: 9467380
    Abstract: A data center network flow migration method includes detecting a utilized loading value in each switch of a plurality of switches in the data center network by a controller according to topology information of the data center network. The controller re-establishes a plurality of link paths corresponding to the plurality of switches in the data center network according to the utilized loading value in each switch and a disjoint edge node divided spanning tree algorithm. In these re-established link paths corresponding to the plurality of switches in the data center network, if the utilized loading value of at least one link path is greater than a threshold value, the at least one link paths with the utilized loading value greater than the threshold value is rerouted by a controller according to a flow migration algorithm.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: October 11, 2016
    Assignees: Inventec (Pudong) Technology Corp., Inventec Corporation
    Inventors: Wei-Fan Hong, Kuo-Chen Wang, Yu-Chun Yeh, Dean-Chung Wang, Ping-Liang Lin
  • Publication number: 20160291341
    Abstract: A laser pulse modulation device is disclosed and includes a first laser source, a second laser source, and a polarizing beam splitter. The first laser source is used to generate a first linearly-polarized pulsed laser beam which oscillates in a direction parallel to a propagation direction thereof. The second laser source is used to generate a second linearly-polarized pulsed laser beam which oscillates in a direction perpendicular to a propagation direction thereof. The polarizing beam splitter is used to overlay the first linearly-polarized pulsed laser beam and the second linearly-polarized pulsed laser beam to form a first combined pulsed laser beam.
    Type: Application
    Filed: April 3, 2015
    Publication date: October 6, 2016
    Inventor: Yu-Chun Yeh
  • Patent number: 9443986
    Abstract: A thin file transistor includes a gate electrode, a source electrode, a drain electrode, a gate-insulating layer, and an oxide semiconductor layer. The oxide semiconductor layer includes indium-gallium-zinc oxide with a formula of InxGayZnzOw, in which x, y and z satisfy the following formulas 1.5?(y/x)?2 and 1.5?(y/z)?2. The gate-insulating layer is positioned between the gate electrode and the oxide semiconductor layer. The source electrode and the drain electrode are respectively connected to two different sides of the oxide semiconductor layer.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: September 13, 2016
    Assignee: E Ink Holdings Inc.
    Inventors: Chih-Hsuan Wang, Chia-Chun Yeh, Ted-Hong Shinn
  • Patent number: D770399
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: November 1, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Hui-Chun Yeh, Chien-Fu Shen, Tsun-Kai Ko
  • Patent number: D770400
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: November 1, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Hui-Chun Yeh, Chien-Fu Shen, Tsun-Kai Ko
  • Patent number: D773410
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: December 6, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Hui-Chun Yeh, Chien-Fu Shen, Tsun-Kai Ko