Patents by Inventor Chun-Ying Lin
Chun-Ying Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136183Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Inventors: Yu-Shih Wang, Hong-Jie Yang, Chia-Ying Lee, Po-Nan Yeh, U-Ting Chiu, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
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Patent number: 11955579Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of light-emitting elements on a first substrate and forming a first pattern array on a second substrate, wherein the first pattern array includes an adhesive layer. The method also includes transferring the plurality of light-emitting elements from the first substrate to the second substrate and forming the first pattern array on a third substrate. The method includes transferring the plurality of light-emitting elements from the second substrate to the third substrate, and reducing an adhesion force of a portion of the adhesive layer. The method also includes forming a second pattern array on a fourth substrate, and transferring the plurality of light-emitting elements from the third substrate to the fourth substrate. The pitch between the plurality of light-emitting elements on the first substrate is different than the pitch of the first pattern array.Type: GrantFiled: April 21, 2022Date of Patent: April 9, 2024Assignee: INNOLUX CORPORATIONInventors: Kai Cheng, Tsau-Hua Hsieh, Fang-Ying Lin, Tung-Kai Liu, Hui-Chieh Wang, Chun-Hsien Lin, Jui-Feng Ko
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Patent number: 11949040Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of diodes on a first substrate and forming a first pattern array on a second substrate. The method also includes transferring the plurality of diodes from the first substrate to the second substrate. The method further includes forming the first pattern array on a third substrate. In addition, the method includes transferring the plurality of diodes from the second substrate to the third substrate. The method also includes forming a second pattern array on a fourth substrate. The method further includes transferring the plurality of diodes from the third substrate to the fourth substrate. The pitch between the plurality of diodes on the first substrate is different from the pitch of the first pattern array.Type: GrantFiled: April 21, 2022Date of Patent: April 2, 2024Assignee: INNOLUX CORPORATIONInventors: Kai Cheng, Tsau-Hua Hsieh, Fang-Ying Lin, Tung-Kai Liu, Hui-Chieh Wang, Chun-Hsien Lin, Jui-Feng Ko
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Publication number: 20240107776Abstract: An antiferroelectric field effect transistor (Anti-FeFET) of a memory cell includes an antiferroelectric layer instead of a ferroelectric layer. The antiferroelectric layer may operate based on a programmed state and an erased state in which the antiferroelectric layer is in a fully polarized alignment and a non-polarized alignment (or a random state of polarization), respectively. This enables the antiferroelectric layer in the FeFET to provide a sharper/larger voltage drop for an erase operation of the FeFET (e.g., in which the FeFET switches or transitions from the programmed state to the erased state) relative to a ferroelectric material layer that operates based on switching between two opposing fully polarized states.Type: ApplicationFiled: January 5, 2023Publication date: March 28, 2024Inventors: Chun-Chieh LU, Chih-Yu CHANG, Yu-Chuan SHIH, Huai-Ying HUANG, Yu-Ming LIN
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Patent number: 11935728Abstract: In order to reduce the occurrence of current alarms in a semiconductor etching or deposition process, a controller determines an offset in relative positions of a cover ring and a shield over a wafer within a vacuum chamber. The controller provides a position alarm and/or adjusts the position of the cover ring or shield when the offset is greater than a predetermined value or outside a range of acceptable values.Type: GrantFiled: January 5, 2021Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Cheng Wu, Sheng-Ying Wu, Ming-Hsien Lin, Chun Fu Chen
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Patent number: 10535593Abstract: A package structure including a circuit substrate, a semiconductor die, a redistribution layer, a plurality of conductive balls and a circuit substrate is provided. The redistribution layer is disposed on the semiconductor die, and being electrically connected to the semiconductor die. The plurality of conductive balls is disposed between the redistribution layer and the circuit substrate. The semiconductor die is electrically connected to the circuit substrate through the conductive balls. Each of the conductive balls has a ball foot with a first width D1, a ball head with a third width D3 and a ball waist with a second width D2 located between the ball foot and the ball head. The ball foot is connected to the redistribution layer, the ball head is connected to the circuit substrate, and the ball waist is the narrowest portion of each of the conductive balls.Type: GrantFiled: April 29, 2019Date of Patent: January 14, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pi-Lan Chang, Chen-Shien Chen, Chin-Yu Ku, Hsu-Hsien Chen, Wei-Chih Huang, Chun-Ying Lin, Li-Chieh Chou
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Publication number: 20190252304Abstract: A package structure including a circuit substrate, a semiconductor die, a redistribution layer, a plurality of conductive balls and a circuit substrate is provided. The redistribution layer is disposed on the semiconductor die, and being electrically connected to the semiconductor die. The plurality of conductive balls is disposed between the redistribution layer and the circuit substrate. The semiconductor die is electrically connected to the circuit substrate through the conductive balls. Each of the conductive balls has a ball foot with a first width D1, a ball head with a third width D3 and a ball waist with a second width D2 located between the ball foot and the ball head. The ball foot is connected to the redistribution layer, the ball head is connected to the circuit substrate, and the ball waist is the narrowest portion of each of the conductive balls.Type: ApplicationFiled: April 29, 2019Publication date: August 15, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pi-Lan Chang, Chen-Shien Chen, Chin-Yu Ku, Hsu-Hsien Chen, Wei-Chih Huang, Chun-Ying Lin, Li-Chieh Chou
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Patent number: 10276481Abstract: A package structure including a circuit substrate, a semiconductor die, a redistribution layer, a plurality of conductive balls and a circuit substrate is provided. The redistribution layer is disposed on the semiconductor die, and being electrically connected to the semiconductor die. The plurality of conductive balls is disposed between the redistribution layer and the circuit substrate. The semiconductor die is electrically connected to the circuit substrate through the conductive balls. Each of the conductive balls has a ball foot with a first width D1, a ball head with a third width D3 and a ball waist with a second width D2 located between the ball foot and the ball head. The ball foot is connected to the redistribution layer, the ball head is connected to the circuit substrate, and the ball waist is the narrowest portion of each of the conductive balls.Type: GrantFiled: October 31, 2017Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pi-Lan Chang, Chen-Shien Chen, Chin-Yu Ku, Hsu-Hsien Chen, Wei-Chih Huang, Chun-Ying Lin, Li-Chieh Chou
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Publication number: 20180374785Abstract: A package structure including a circuit substrate, a semiconductor die, a redistribution layer, a plurality of conductive balls and a circuit substrate is provided. The redistribution layer is disposed on the semiconductor die, and being electrically connected to the semiconductor die. The plurality of conductive balls is disposed between the redistribution layer and the circuit substrate. The semiconductor die is electrically connected to the circuit substrate through the conductive balls. Each of the conductive balls has a ball foot with a first width D1, a ball head with a third width D3 and a ball waist with a second width D2 located between the ball foot and the ball head. The ball foot is connected to the redistribution layer, the ball head is connected to the circuit substrate, and the ball waist is the narrowest portion of each of the conductive balls.Type: ApplicationFiled: October 31, 2017Publication date: December 27, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pi-Lan Chang, Chen-Shien Chen, Chin-Yu Ku, Hsu-Hsien Chen, Wei-Chih Huang, Chun-Ying Lin, Li-Chieh Chou
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Patent number: 9328930Abstract: A range hood with an easily assembled and disassembled lamp includes a main body, a lamp seat, a lamp plug, a lamp, and a fastening device. Therein, the main body has a bottom board having an outer surface and an opposite inner surface with a combining hole in between. The lamp seat, with a lighting hole, rotationally moves between a first position and a second position for being longitudinally detached from the combining hole. The lamp plug is disposed on one side of the inner surface. The lamp has one end held by the lamp seat and the other end coupled to the lamp plug. The fastening device has one end connected to the lamp plug for attaching the lamp to the lamp seat. Thus, the lamp of the range hood is easily assembled or disassembled.Type: GrantFiled: February 13, 2014Date of Patent: May 3, 2016Assignee: LONG INDUSTRY INC.Inventor: Chun-Ying Lin
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Publication number: 20150184869Abstract: A range hood with an easily assembled and disassembled lamp includes a main body, a lamp seat, a lamp plug, a lamp, and a fastening device. Therein, the main body has a bottom board having an outer surface and an opposite inner surface with a combining hole in between. The lamp seat, with a lighting hole, rotationally moves between a first position and a second position for being longitudinally detached from the combining hole. The lamp plug is disposed on one side of the inner surface. The lamp has one end held by the lamp seat and the other end coupled to the lamp plug. The fastening device has one end connected to the lamp plug for attaching the lamp to the lamp seat. Thus, the lamp of the range hood is easily assembled or disassembled.Type: ApplicationFiled: February 13, 2014Publication date: July 2, 2015Applicant: LONG INDUSTRY INC.Inventor: Chun-Ying LIN
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Patent number: 8106494Abstract: A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins.Type: GrantFiled: January 28, 2011Date of Patent: January 31, 2012Assignee: Chipmos Technologies Inc.Inventors: Chun Ying Lin, Geng Shin Shen, Yu Tang Pan, Shih Wen Chou
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Patent number: 8105876Abstract: A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins.Type: GrantFiled: January 28, 2011Date of Patent: January 31, 2012Assignee: Chipmos Technologies Inc.Inventors: Chun Ying Lin, Geng Shin Shen, Yu Tang Pan, Shih Wen Chou
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Patent number: 8048778Abstract: An embodiment of the disclosure includes a method of dicing a semiconductor structure. A device layer on a semiconductor substrate is provided. The device layer has a first chip region and a second chip region. A scribe line region is between the first chip region and the second chip region. A protective layer is formed over the device layer thereby over the semiconductor substrate. The protective layer on the scribe line region is laser sawn to form a notch. The notch extends into the semiconductor substrate and the protective layer is formed to cover a portion of the notch. A mechanically sawing is performed through the portion of the protective layer and the substrate to separate the first chip region and the second chip region.Type: GrantFiled: December 10, 2010Date of Patent: November 1, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Yu Ku, Hsiu-Mei Yu, Chun-Ying Lin, Young-Chang Lien, Sheng-Hsiang Chiu, Ta-Jen Yu
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Publication number: 20110133322Abstract: A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins.Type: ApplicationFiled: January 28, 2011Publication date: June 9, 2011Applicant: CHIPMOS TECHNOLOGIES INC.Inventors: Chun Ying Lin, Geng Shin Shen, Yu Tang Pan, Shih Wen Chou
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Publication number: 20110136299Abstract: A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins.Type: ApplicationFiled: January 28, 2011Publication date: June 9, 2011Applicant: CHIPMOS TECHNOLOGIES INC.Inventors: Chun Ying Lin, Geng Shin Shen, Yu Tang Pan, Shih Wen Chou
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Publication number: 20110124742Abstract: The present invention is related to a composition and method of adipose cell differentiation inhibition.Type: ApplicationFiled: January 31, 2011Publication date: May 26, 2011Applicants: NATIONAL YANG-MING UNIVERSITY, YANGSON BIOTECHNOLOGY CO., LTD.Inventors: MENG-HWAN LEE, JUNG-WEI TSAI, YUN-YU CHEN, YING-CHIEH TSAI, CHUN-YING LIN
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Patent number: 7932531Abstract: A chip package includes a thermal enhanced plate, contacts around the thermal enhanced plate and electrically insulated from the thermal enhanced plate, a film-like circuit layer disposed on the contacts and the thermal enhanced plate, a conductive adhesive layer, a first molding, and at least one chip disposed on the film-like circuit layer. The conductive adhesive layer is disposed between the contacts and the film-like circuit layer electrically connected to the contacts through the conductive adhesive layer. The chip has a back surface, an active surface and many bumps disposed thereon, and the chip is electrically connected to the film-like circuit layer via the bumps. The first molding at least encapsulates a portion of the thermal enhanced plate, the conductive adhesive layer, parts of the contacts and at least a portion of the film-like circuit layer. Therefore, heat dissipation efficiency of the light emitting chip package is improved.Type: GrantFiled: July 21, 2009Date of Patent: April 26, 2011Assignee: ChipMOS Technologies Inc.Inventors: Chun-Ying Lin, Ya-Chi Chen, Yu-Ren Chen, I-Hsin Mao
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Patent number: 7902649Abstract: A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins.Type: GrantFiled: November 2, 2007Date of Patent: March 8, 2011Assignee: Chipmos Technologies Inc.Inventors: Chun Ying Lin, Geng Shin Shen, Yu Tang Pan, Shih Wen Chou
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Patent number: 7851262Abstract: A manufacturing process for a chip package structure is provided. First, a patterned conductive layer and a patterned solder resist layer on the patterned conductive layer are provided. A plurality of chips are bonded onto the patterned conductive layer such that the chips and the patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer. A molding compound is formed to encapsulate the patterned conductive layer, the chips and the bonding wires. Then, the molding compound, the patterned conductive layer and the patterned solder resist layer are separated.Type: GrantFiled: November 13, 2008Date of Patent: December 14, 2010Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.Inventors: Geng-Shin Shen, Chun-Ying Lin