Abstract: A package structure including a circuit substrate, a semiconductor die, a redistribution layer, a plurality of conductive balls and a circuit substrate is provided. The redistribution layer is disposed on the semiconductor die, and being electrically connected to the semiconductor die. The plurality of conductive balls is disposed between the redistribution layer and the circuit substrate. The semiconductor die is electrically connected to the circuit substrate through the conductive balls. Each of the conductive balls has a ball foot with a first width D1, a ball head with a third width D3 and a ball waist with a second width D2 located between the ball foot and the ball head. The ball foot is connected to the redistribution layer, the ball head is connected to the circuit substrate, and the ball waist is the narrowest portion of each of the conductive balls.

Abstract: A package structure including a circuit substrate, a semiconductor die, a redistribution layer, a plurality of conductive balls and a circuit substrate is provided. The redistribution layer is disposed on the semiconductor die, and being electrically connected to the semiconductor die. The plurality of conductive balls is disposed between the redistribution layer and the circuit substrate. The semiconductor die is electrically connected to the circuit substrate through the conductive balls. Each of the conductive balls has a ball foot with a first width D1, a ball head with a third width D3 and a ball waist with a second width D2 located between the ball foot and the ball head. The ball foot is connected to the redistribution layer, the ball head is connected to the circuit substrate, and the ball waist is the narrowest portion of each of the conductive balls.

Abstract: A package structure including a circuit substrate, a semiconductor die, a redistribution layer, a plurality of conductive balls and a circuit substrate is provided. The redistribution layer is disposed on the semiconductor die, and being electrically connected to the semiconductor die. The plurality of conductive balls is disposed between the redistribution layer and the circuit substrate. The semiconductor die is electrically connected to the circuit substrate through the conductive balls. Each of the conductive balls has a ball foot with a first width D1, a ball head with a third width D3 and a ball waist with a second width D2 located between the ball foot and the ball head. The ball foot is connected to the redistribution layer, the ball head is connected to the circuit substrate, and the ball waist is the narrowest portion of each of the conductive balls.

Abstract: A package structure including a circuit substrate, a semiconductor die, a redistribution layer, a plurality of conductive balls and a circuit substrate is provided. The redistribution layer is disposed on the semiconductor die, and being electrically connected to the semiconductor die. The plurality of conductive balls is disposed between the redistribution layer and the circuit substrate. The semiconductor die is electrically connected to the circuit substrate through the conductive balls. Each of the conductive balls has a ball foot with a first width D1, a ball head with a third width D3 and a ball waist with a second width D2 located between the ball foot and the ball head. The ball foot is connected to the redistribution layer, the ball head is connected to the circuit substrate, and the ball waist is the narrowest portion of each of the conductive balls.

Abstract: A range hood with an easily assembled and disassembled lamp includes a main body, a lamp seat, a lamp plug, a lamp, and a fastening device. Therein, the main body has a bottom board having an outer surface and an opposite inner surface with a combining hole in between. The lamp seat, with a lighting hole, rotationally moves between a first position and a second position for being longitudinally detached from the combining hole. The lamp plug is disposed on one side of the inner surface. The lamp has one end held by the lamp seat and the other end coupled to the lamp plug. The fastening device has one end connected to the lamp plug for attaching the lamp to the lamp seat. Thus, the lamp of the range hood is easily assembled or disassembled.

Abstract: A range hood with an easily assembled and disassembled lamp includes a main body, a lamp seat, a lamp plug, a lamp, and a fastening device. Therein, the main body has a bottom board having an outer surface and an opposite inner surface with a combining hole in between. The lamp seat, with a lighting hole, rotationally moves between a first position and a second position for being longitudinally detached from the combining hole. The lamp plug is disposed on one side of the inner surface. The lamp has one end held by the lamp seat and the other end coupled to the lamp plug. The fastening device has one end connected to the lamp plug for attaching the lamp to the lamp seat. Thus, the lamp of the range hood is easily assembled or disassembled.

Abstract: A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins.

Abstract: A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins.

Abstract: An embodiment of the disclosure includes a method of dicing a semiconductor structure. A device layer on a semiconductor substrate is provided. The device layer has a first chip region and a second chip region. A scribe line region is between the first chip region and the second chip region. A protective layer is formed over the device layer thereby over the semiconductor substrate. The protective layer on the scribe line region is laser sawn to form a notch. The notch extends into the semiconductor substrate and the protective layer is formed to cover a portion of the notch. A mechanically sawing is performed through the portion of the protective layer and the substrate to separate the first chip region and the second chip region.

Abstract: A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins.

Abstract: A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins.

Abstract: The present invention is related to a composition and method of adipose cell differentiation inhibition.

Abstract: A chip package includes a thermal enhanced plate, contacts around the thermal enhanced plate and electrically insulated from the thermal enhanced plate, a film-like circuit layer disposed on the contacts and the thermal enhanced plate, a conductive adhesive layer, a first molding, and at least one chip disposed on the film-like circuit layer. The conductive adhesive layer is disposed between the contacts and the film-like circuit layer electrically connected to the contacts through the conductive adhesive layer. The chip has a back surface, an active surface and many bumps disposed thereon, and the chip is electrically connected to the film-like circuit layer via the bumps. The first molding at least encapsulates a portion of the thermal enhanced plate, the conductive adhesive layer, parts of the contacts and at least a portion of the film-like circuit layer. Therefore, heat dissipation efficiency of the light emitting chip package is improved.

Abstract: A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins.

Abstract: A manufacturing process for a chip package structure is provided. First, a patterned conductive layer and a patterned solder resist layer on the patterned conductive layer are provided. A plurality of chips are bonded onto the patterned conductive layer such that the chips and the patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer. A molding compound is formed to encapsulate the patterned conductive layer, the chips and the bonding wires. Then, the molding compound, the patterned conductive layer and the patterned solder resist layer are separated.

Abstract: A Quad Flat Non-leaded (QFN) chip package including a patterned conductive layer, a first solder resist layer, a chip, a plurality of bonding wires and a molding compound is provided. The patterned conductive layer has a first surface and a second surface opposite to each other. The first solder resist layer is disposed on the first surface, wherein a part of the first surface is exposed by the first solder resist layer. The chip is disposed on the first solder resist layer, wherein the first solder resist layer is between the patterned conductive layer and the chip. The bonding wires are electrically connected to the chip and the patterned conductive layer exposed by the first solder resist layer. The molding compound encapsulates the pattern conductive layer, the first solder resist layer, the chip and the bonding wires.

Abstract: A manufacturing process for a chip package structure is provided. First, a patterned conductive layer having a plurality of first openings and a patterned solder resist layer on the patterned conductive layer are provided. A plurality of chips are bonded onto the patterned conductive layer such that the chips and the patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires passing through the first openings of the patterned conductive layer. At least one molding compound is formed to encapsulate the patterned conductive layer, the patterned solder resist layer, the chips and the bonding wires. Then, the molding compound, the patterned conductive layer and the patterned solder resist layer are separated.

Abstract: A method of fabricating a quad flat non-leaded package includes first forming a patterned conductive layer on a sacrificial layer. The patterned conductive layer includes a number of lead sets. A number of chips are attached to the sacrificial layer. Each of the chips is surrounded by one of the lead sets. Each of the chips is electrically connected to one of the lead sets, and a molding compound is formed on the sacrificial layer to cover the patterned conductive layer and the chips. The molding compound and the patterned conductive layer are then cut and singulated, and the sacrificial layer is pre-cut to form a number of recesses on the sacrificial layer. After the molding compound and the patterned conductive layer are cut and singulated and the sacrificial layer is pre-cut, the sacrificial layer is removed.

Abstract: A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure is provided. First, a conductive layer having recesses and a patterned solder resist layer on the conductive layer are provided, wherein the patterned solder resist layer covers the recesses of the conductive layer. A part of the conductive layer uncovered by the patterned solder resist layer is removed so as to form a patterned conductive layer. Chips are bonded onto the patterned conductive layer such that the patterned solder resist layer and the chips are at the same side of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer. At least one molding compound is formed and the molding compound and the patterned conductive layer are separated.