Abstract: A test system includes a host, a module to communicate with the host, and a test device to test the module while the module is connected to the host. The host includes a pulse width modulator circuit to supply a power to the module, and the test device varies a feedback resistance value provided to the pulse width modulator circuit.

Abstract: The present invention relates to a chip-type protection device having an enclosed micro-gap between electrodes. The invention includes a substrate on which a pair of discharge electrodes extend towards each other by a micro-gap. A wall is disposed in a manner spaced apart from the micro-gaps by a predetermined distance, on which a cover portion is mounted in a straddling manner across the micro-gaps. The wall and the cover portion are integrated under a predetermined gaseous environment to form a hermectic chamber on which an outer protective layer is coated. End electrodes are subsequently formed on the substrate in a manner connected to conductive portions of the discharge electrodes. The invention provides a protection device against over-voltage.

Abstract: The invention provides a method of test pattern generation for an integrated circuit (IC) design simulation system, comprising merging at least 2 test vectors into a merged vector, wherein each test defines a set of test behaviors, and compiling and linking the merged vector using the IC design simulation system to generate a merged test pattern able to perform each set of test behaviors independently.

Abstract: A thin film transistor substrate and a method of manufacturing the TFT substrate that are capable of simplifying manufacturing processes and protecting a gate driver from being eroded. The thin film transistor substrate includes an insulation substrate including a display area and a non-display area, a gate metal pattern including a first gate electrode formed on the insulation substrate in the display region, a gate insulation layer formed on the gate metal pattern, a first semiconductor pattern formed on the gate insulation layer overlapping the first gate electrode, a data metal pattern including a first source electrode and a first drain electrode that are connected to both ends of the first semiconductor pattern, a transparent conductive pattern connected to the first drain electrode and formed on the gate insulation layer, and a protective layer formed on the first semiconductor pattern and the data metal pattern.

Abstract: The invention provides a method of test pattern generation for an integrated circuit (IC) design simulation system, comprising merging at least 2 test vectors into a merged vector, wherein each test defines a set of test behaviors, and compiling and linking the merged vector using the IC design simulation system to generate a merged test pattern able to perform each set of test behaviors independently.

Abstract: Disclosed are a thin film transistor (TFT) substrate capable of preventing separation between an organic layer and an inorganic layer, a method of fabricating the TFT substrate, an LCD panel having the TFT substrate, and a method of fabricating the LCD panel. The TFT thin film transistor substrate includes a TFT connected to a gate line and a data line, an organic protective layer for protecting the thin film transistor, and an inorganic insulating layer formed between the gate line and the data line. The inorganic insulating layer is formed such that a contact surface with the organic protective layer has a different pattern from a non-contact surface with the organic protective layer.

Abstract: A thin film transistor substrate having improved display quality includes a gate line, a data line intersecting the gate line and providing a pixel region adjacent the gate line and the data line, a data pattern formed on substantially a same plane and of substantially a same metal as the data line, a thin film transistor connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, an organic protective layer formed under the pixel electrode and protecting the thin film transistor, and an inorganic protective layer formed between the data pattern and the organic protective layer, the inorganic protective layer formed on the data pattern with a pattern similar to the data pattern. A manufacturing method of the above-described thin film transistor substrate is further provided.

Abstract: Provided are a thin film transistor (TFT) capable of increasing ON current and decreasing OFF current values, a TFT substrate having the polysilicon TFT, a method of fabricating the polysilicon TFT, and a method of fabricating a TFT substrate having the polysilicon TFT. The polysilicon TFT substrate includes a gate line and a data line defining a pixel region, a pixel electrode formed in the pixel region, and a TFT including a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode connected to the pixel electrode, and a polysilicon active layer forming a channel between the source and drain electrodes. The polysilicon active layer includes a channel region on which the gate electrode is superposed, source and drain regions connected to the source and drain electrode, respectively, and at least two lightly doped drain (LDD) regions y formed between the source region and the channel region and between the drain region and the channel region.