Abstract: A vehicle air conditioner, wherein an air conditioner of an integrated heat pump system enables the improvement of cold air and warm air mixing characteristics so as to decrease left-right temperature differences, enables the implementation of independent left-right air conditioning, and enables the sufficient securement of an interior space of the vehicle.

Abstract: Some embodiments relate to a semiconductor structure having a magnetic tunnel junction (MTJ) on a substrate and a top electrode on the MTJ. A first segment of a top surface of the top electrode adjacent to a first sidewall of the top electrode is different from a second segment of the top surface of the top electrode adjacent to a second sidewall of the top electrode. A sidewall spacer comprises a first spacer on the first sidewall of the top electrode and a second spacer on the second sidewall of the top electrode. A first surface of the first spacer comprises a first curve and a second surface of the second spacer comprises a second curve. A dielectric layer is around the MTJ and top electrode.

Abstract: Disclosed is a vehicle air conditioner, wherein an integrated air conditioning module using a heat pump system enables, in order to secure interior space, the optimizing of the arrangement thereof and the arrangements among the elements thereof, and the increasing of a coupling force between an air conditioning module and a distribution duct.

Abstract: Systems with a contouring method are provided for contouring one or more targets that correspond to specific organs and/or tumors in a three-dimensional medical image of a patient using neural networks. The contouring system includes a storage unit, a processing unit, and a plurality of modules that are computer operable. The processing unit is used to obtain the image, and then to generate one or more contouring images using a contouring method. The contouring method includes enhancing image features and improving contouring accuracy using an image preprocessing module, and extracting a plurality of multi-scale image representations and expanding these representations to one or more contouring images using a neural network-based contouring module.

Abstract: An MRAM memory cell includes a substrate and a transistor. The transistor includes: first and second source regions; a drain region between the first and second source regions; a first channel region between the drain region and the first source region; a second channel region between the drain region and the second source region; a first gate structure over the first channel region; and a second gate structure over the second channel region. A magnetic tunnel junction is overlying the transistor. The drain region is coupled to the magnetic tunnel junction. A first metal layer is overlying the transistor, and a second metal layer is overlying the first metal layer. The second and first metal layers couple a common source line signal to the first and second source regions of the MRAM memory cell and to those of a neighboring MRAM memory cell.

Abstract: The present disclosure provides a system and method for forming a reduced area MRAM memory cell including a substrate, a transistor overlying the substrate and a magnetic tunnel junction overlying the transistor. The transistor includes a first and second source regions, a drain region between the first and second source regions, at least one first channel region between the drain region and the first source region, at least one second channel region between the drain region and the second source region, a first gate structure overlying the at least one first channel region, and a second gate structure overlying the at least one second channel region. First and second metal layers overlie the transistor. The first and second metal layers are configured to couple a common source line signal to the first and second source regions.

Abstract: Some embodiments relate to an integrated chip having a memory cell overlying a substrate and comprising a top electrode. A top electrode via overlies the top electrode. A width of an upper surface of the top electrode via is greater than a width of an upper surface of the top electrode. A conductive via overlies the top electrode via. A width of an upper surface of the conductive via is greater than the width of the upper surface of the top electrode via.

Abstract: A method for preparing glucosamine includes the steps of converting fructose-6-phosphate (F6P) and an ammonium salt to glucosamine-6-phosphate (GlcN6P) under the catalysis of glucosamine-6-phosphate deaminase (EC 3.5.99.6, GlmD); and producing glucosamine (GlcN) by the dephosphorylation of GlcN6P under the catalysis of an enzyme capable of catalyzing the dephosphorylation. Such a method can be used to prepare glucosamine by in vitro enzymatic biosystem.

Abstract: Recombinant strains are obtained for the production of allulose, allose, and allitol by regulating intracellular glucose metabolism, reducing the enzyme activity of fructose 6-phosphate kinase, and enhancing the enzyme activities of glucokinase and glucose-6-phosphate isomerase, allulose 6-phosphate 3-epimerase, allulose 6-phosphate phosphatase, fructose permease and fructokinase, and optionally enhancing the enzyme activities of ribose 5-phosphate isomerase, allose 6-phosphate phosphatase, ribitol dehydrogenase, glycerol permease, glycerol dehydrogenase, and dihydroxyacetone kinase. A method for producing allulose and allose is an extracellular multienzyme cascade method. Multienzyme cascade catalysis and fermentation are coupled to improve the conversion rate of starch sugar or sucrose to the synthesized allulose.

Abstract: Some embodiments relate to a method for manufacturing a memory device. The method includes forming a first masking layer disposed over a dielectric layer, the first masking layer exhibiting sidewalls defining an opening disposed above a magnetoresistive random-access memory (MRAM) cell located in an embedded memory region. A first etch is performed to form a first via opening within the dielectric layer above the MRAM cell. A top electrode via layer formed over the MRAM cell and the dielectric layer. A first planarization process performed on the top electrode via layer to remove part of the top electrode via layer and define a top electrode via having a substantially flat top surface.

Abstract: Some embodiments relate to a magnetoresistive random-access memory (MRAM) cell. The cell includes a bottom electrode having a central bottom electrode portion surrounded by a peripheral bottom electrode portion. Step regions of the conductive bottom electrode couple the central and peripheral bottom electrode portions to one another such that an upper surface of the central portion is recessed relative to an upper surface of the peripheral portion. A magnetic tunneling junction (MTJ) has MTJ outer sidewalls which are disposed over the bottom central electrode portion and which are arranged between the step regions. A top electrode is disposed over an upper surface of the MTJ. Other devices and methods are also disclosed.

Abstract: An inositol preparation method by enzymatic catalysis uses starch and cellulose or substrates thereof as substrates. Raw materials are converted to inositol by in vitro multi-enzyme reaction system in one pot. The yield from the substrate to inositol is significantly improved by process optimization and adding new enzymes. The new enzymes can promote the phosphorolysis of starch or cellulose and utilization of glucose, which is the final production after the phosphorolysis of starch and cellulose. The inositol preparation method described herein has great potentials in industrial production of inositol because of high inositol yield, easy scale-up, low production cost, and lower impact to environment.

Abstract: Some embodiments relate to a magnetoresistive random-access memory (MRAM) cell. The cell includes a bottom electrode having a central bottom electrode portion surrounded by a peripheral bottom electrode portion. Step regions of the conductive bottom electrode couple the central and peripheral bottom electrode portions to one another such that an upper surface of the central portion is recessed relative to an upper surface of the peripheral portion. A magnetic tunneling junction (MTJ) has MTJ outer sidewalls which are disposed over the bottom central electrode portion and which are arranged between the step regions. A top electrode is disposed over an upper surface of the MTJ. Other devices and methods are also disclosed.

Abstract: Disclosed is a vehicle air conditioner, wherein an air conditioner of an integrated heat pump system enables the improvement of cold air and warm air mixing characteristics so as to decrease left-right temperature differences, enables the implementation of independent left-right air conditioning, and enables the sufficient securement of an interior space.

Abstract: The present disclosure provides a system and method for forming a reduced area MRAM memory cell including a substrate, a transistor overlying the substrate and a magnetic tunnel junction overlying the transistor. The transistor includes a first and second source regions, a drain region between the first and second source regions, at least one first channel region between the drain region and the first source region, at least one second channel region between the drain region and the second source region, a first gate structure overlying the at least one first channel region, and a second gate structure overlying the at least one second channel region. First and second metal layers overlie the transistor. The first and second metal layers are configured to couple a common source line signal to the first and second source regions.

Abstract: Various embodiments of the present application are directed towards a one-time-programmable (OTP) implementation using magnetic junctions. In some embodiments, an array comprises multiple magnetic junctions in multiple columns and multiple rows, and the magnetic junctions comprise a first magnetic junction and a second magnetic junction. The first and second magnetic junctions comprise individual top ferromagnetic elements and individual bottom ferromagnetic elements, and further comprise individual barrier elements between the top and bottom ferromagnetic elements. A first barrier element of the first magnetic junction electrically separates first top and bottom ferromagnetic elements of the first magnetic junction. A second barrier element of the second magnetic junction has undergone breakdown, such that it has defects defining a leakage path between second top and bottom ferromagnetic elements of the second magnetic junction.

Abstract: A storage device includes: a plurality of first magnetic tunnel junction (MTJ) cells disposed on a first portion of a substrate; and a plurality of second MTJ cells disposed on a second portion different from the first portion of the substrate; wherein each of the plurality of first MTJ cells has a first cross-sectional surface area viewing from a top of the substrate, each of the plurality of second MTJ cells has a second cross-sectional surface area viewing from the top of the substrate, and the second cross-sectional surface area is greater than the first cross-sectional surface area.

Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, protection spacers and a second electrode. The first electrode has a top surface and a first outer sidewall surface on the memory region. The resistance variable layer has a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection spacers are disposed over a portion of the top surface of the first electrode and surround the second portion of the resistance variable layer. The protection spacers are configurable to protect at least one conductive path in the resistance variable layer. The protection spacers have a second outer sidewall surface substantially aligned with the first outer sidewall surface of the first electrode.