Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell. The method forms a bottom electrode over a bottom electrode via. The method further forms a variable resistive dielectric layer over the bottom electrode, and a top electrode over the variable resistive dielectric layer. The method forms a top electrode via vertically extending outward from an upper surface of the top electrode at a position centered along a first axis that is laterally offset from a second axis centered upon the bottom electrode via. The top electrode via has a smaller width than the top electrode. Laterally offsetting the top electrode via from the bottom electrode via provides the top electrode via with good contact resistance.

Abstract: The present disclosure discloses method and device for prompting program uninstallation and belongs to the field of the Internet. The method comprises: performing a security assessment of an application program installed on a mobile terminal, thereby obtaining a security assessment result; obtaining security identification information corresponding to the security assessment result based on pre-stored correlations between security assessment results and security identification information; establishing a correlation between the obtained security identification information and the application program, and displaying the correlation to a user.

Abstract: One embodiment in the present disclosure provides a resistor in a resistive random access memory (RRAM). The resistor includes a first electrode; a resistive layer on the first electrode; an electric field enhancement array in the resistive layer; and a second electrode on the resistive layer. The electric field enhancement array includes a plurality of electric field enhancers arranged in a same plane. One embodiment in the present disclosure provides a method of manufacturing a resistor structure in an RRAM. The method comprises (1) forming a first resistive layer on a first electrode; (2) forming a metal layer on the resistive layer; (3) patterning the metal layer to form a metal dot array on the resistive layer; and (4) forming a second electrode on the metal dot array. The metal dot array comprises a plurality of metal dots, and a distance between adjacent metal dots is less than 40 nm.

Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, protection spacers and a second electrode. The first electrode has a top surface and a first outer sidewall surface on the memory region. The resistance variable layer has a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection spacers are disposed over a portion of the top surface of the first electrode and surround the second portion of the resistance variable layer. The protection spacers are configurable to protect at least one conductive path in the resistance variable layer. The protection spacers have a second outer sidewall surface substantially aligned with the first outer sidewall surface of the first electrode.

Abstract: Some embodiments relate to an integrated circuit device. The integrated circuit device includes a resistive random access memory (RRAM) cell, which includes a top electrode and a bottom electrode that are separated by a RRAM dielectric layer. The top electrode of the RRAM cell has a recess in its upper surface. A via is disposed over the RRAM cell and contacts the top electrode within the recess.

Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell. The method forms a bottom electrode over a bottom electrode via. The method further forms a variable resistive dielectric layer over the bottom electrode, and a top electrode over the variable resistive dielectric layer. The method forms a top electrode via vertically extending outward from an upper surface of the top electrode at a position centered along a first axis that is laterally offset from a second axis centered upon the bottom electrode via. The top electrode via has a smaller width than the top electrode. Laterally offsetting the top electrode via from the bottom electrode via provides the top electrode via with good contact resistance.

Abstract: An integrated circuit device including a resistive random access memory (RRAM) cell formed over a substrate. The RRAM cell includes a top electrode having an upper surface. A blocking layer covers a portion of the upper surface. A via extends above the top electrode within a matrix of dielectric. The upper surface of the top electrode includes an area that interfaces with the blocking layer and an area that interfaces with the via. The area of the upper surface that interfaces with the via surrounds the area of the upper surface that interfaces with the blocking layer. The blocking layer is functional during processing to protect the RRAM cell from etch damage while being structured in such a way as to not interfere with contact between the overlying via and the top electrode.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) cell architecture, with off-axis or laterally offset top electrode via (TEVA) and bottom electrode via (BEVA). Traditional RRAM cells having a TEVA and BEVA that are on-axis can cause high contact resistance variations. The off-axis TEVA and BEVA in the current disclosure pushes the TEVA away from the insulating layer over the RRAM cell, which can improve the contact resistance variations. The present disclosure also relates to a memory device having a rectangular shaped RRAM cell having a larger area that can lower the forming voltage and improve data retention.

Abstract: A method is disclosed that includes the operations outlined below. A first voltage is applied to a gate of an access transistor of each of a row of memory cells during a reset operation, wherein a first source/drain of the access transistor is electrically connected to a first electrode of a resistive random access memory (RRAM) device in the same memory cell. An inhibition voltage is applied to a second electrode of the RRAM device or to a second source/drain of the access transistor of each of a plurality of unselected memory cells when the first voltage is applied to the gate of the access transistor.

Abstract: A lifting platform includes a base, two “T”-shaped parallel sliding grooves in supporting bars, two wheels, a platform, and a cylinder. Each wheel is held away from the internal far rolling surface of each sliding groove in an original position because of the orientation of the connected platform, but can contact and rest upon the rolling surface and further roll along the rolling surface when the platform is rotated. A hydraulic or air-driven piston rod of the cylinder can push the platform to first rotate and then move upward. The platform is transitionable between: (i) an inclined configuration in which each first wheel is in the original position; (ii) a horizontal configuration in which each first wheel contacts and rests upon a sliding groove; and (iii) a lifting configuration in which each first wheel rolls along a sliding groove.

Abstract: An integrated circuit device including a resistive random access memory (RRAM) cell formed over a substrate. The RRAM cell includes a top electrode having an upper surface. A blocking layer covers a portion of the upper surface. A via extends above the top electrode within a matrix of dielectric. The upper surface of the top electrode includes an area that interfaces with the blocking layer and an area that interfaces with the via. The area of the upper surface that interfaces with the via surrounds the area of the upper surface that interfaces with the blocking layer. The blocking layer is functional during processing to protect the RRAM cell from etch damage while being structured in such a way as to not interfere with contact between the overlying via and the top electrode.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) cell architecture, with off-axis or laterally offset top electrode via (TEVA) and bottom electrode via (BEVA). Traditional RRAM cells having a TEVA and BEVA that are on-axis can cause high contact resistance variations. The off-axis TEVA and BEVA in the current disclosure pushes the TEVA away from the insulating layer over the RRAM cell, which can improve the contact resistance variations. The present disclosure also relates to a memory device having a rectangular shaped RRAM cell having a larger area that can lower the forming voltage and improve data retention.

Abstract: A method is disclosed that includes the operations outlined below. A first voltage is applied to a gate of an access transistor of each of a row of memory cells during a reset operation, wherein a first source/drain of the access transistor is electrically connected to a first electrode of a resistive random access memory (RRAM) device in the same memory cell. An inhibition voltage is applied to a second electrode of the RRAM device or to a second source/drain of the access transistor of each of a plurality of unselected memory cells when the first voltage is applied to the gate of the access transistor.

Abstract: One embodiment in the present disclosure provides a resistor in a resistive random access memory (RRAM). The resistor includes a first electrode; a resistive layer on the first electrode; an electric field enhancement array in the resistive layer; and a second electrode on the resistive layer. The electric field enhancement array includes a plurality of electric field enhancers arranged in a same plane. One embodiment in the present disclosure provides a method of manufacturing a resistor structure in an RRAM. The method comprises (1) forming a first resistive layer on a first electrode; (2) forming a metal layer on the resistive layer; (3) patterning the metal layer to form a metal dot array on the resistive layer; and (4) forming a second electrode on the metal dot array. The metal dot array comprises a plurality of metal dots, and a distance between adjacent metal dots is less than 40 nm.

Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, protection spacers and a second electrode. The first electrode has a top surface and a first outer sidewall surface on the memory region. The resistance variable layer has a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection spacers are disposed over a portion of the top surface of the first electrode and surround at least the second portion of the resistance variable layer. The protection spacers are configurable to protect at least one conductive path in the resistance variable layer. The protection spacers have a second outer sidewall surface substantially aligned with the first outer sidewall surface of the first electrode.

Abstract: An electronic device includes an electronic card connector. The electronic card connector includes a tray assembly configured to receive an electronic card, and a base configured to receive the tray assembly. The tray assembly includes a hook mechanism, and the base includes a hook engaging mechanism. The tray assembly is locked in the base by an engagement of the hook mechanism and the hook engaging mechanism. The base also includes an elastic member. The elastic member is configured to eject the tray assembly out of the base when the hook mechanism is disengaged from the hook engaging mechanism.

Abstract: The present disclosure discloses method and device for prompting program uninstallation and belongs to the field of the Internet. The method comprises: performing a security assessment of an application program installed on a mobile terminal, thereby obtaining a security assessment result; obtaining security identification information corresponding to the security assessment result based on pre-stored correlations between security assessment results and security identification information; establishing a correlation between the obtained security identification information and the application program, and displaying the correlation to a user.

Abstract: This discloses a software-sharing method among terminals. The method includes: receiving a request transmitted by a second terminal to obtain a second shared software installation package; obtaining, in accordance with the shared software ID, a default software installation package corresponding to the shared software ID; generating the second shared software installation package in accordance with the default software installation package and an sharing party ID; transmitting the second installation package to the second terminal, allowing installation at the second terminal the shared software using the second installation package. Also disclosed is a server including: a software installation package acquisition request obtaining module, a shared software installation package transmitting module, a shared software installation package generating module, and a default software installation package obtaining module.

Abstract: The present invention relates to a chip-type protection device having an enclosed micro-gap between electrodes. The invention includes a substrate on which a pair of discharge electrodes extend towards each other by a micro-gap. A wall is disposed in a manner spaced apart from the micro-gaps by a predetermined distance, on which a cover portion is mounted in a straddling manner across the micro-gaps. The wall and the cover portion are integrated under a predetermined gaseous environment to form a hermectic chamber on which an outer protective layer is coated. End electrodes are subsequently formed on the substrate in a manner connected to conductive portions of the discharge electrodes. The invention provides a protection device against over-voltage.

Abstract: A test system includes a host, a module to communicate with the host, and a test device to test the module while the module is connected to the host. The host includes a pulse width modulator circuit to supply a power to the module, and the test device varies a feedback resistance value provided to the pulse width modulator circuit.