Abstract: A transmission device for suppressing the glass-fiber effect includes a circuit board and a transmission line. The circuit board includes a plurality of glass fibers, so as to define a fiber pitch. The transmission line is disposed on the circuit board. The transmission line includes a plurality of non-parallel segments. Each of the non-parallel segments of the transmission line has an offset distance with respect to a reference line. The offset distance is longer than or equal to a half of the fiber pitch.

Abstract: In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.

Abstract: An illumination system provides an illumination beam and includes a red light source, a green light source, a blue light source, a first supplementary light source, a first X-shaped light-splitting assembly, a first light-splitting element, and a light-uniforming element. The red light source provides a red beam. The green light source provides a green beam. The blue light source provides a blue beam. The first supplementary light source provides a first supplementary beam. The first X-shaped light-splitting assembly guides the first supplementary beam and the blue beam to the first light-splitting element. The first light-splitting element guides the red beam, the green beam, the blue beam, and the first supplementary beam to the light-uniforming element. The first supplementary beam is a red supplementary beam or a blue supplementary beam, and the illumination system includes at least five light-emitting elements. A projection apparatus including the above illumination system is also provided.

Abstract: A film manufacturing equipment includes a transporting device, a filtering device, a coating device, a baking device and a blowing device. Transporting device is configured to transport a substrate. The filtering device is configured to filter a solution. The coating device is configured to squeeze and coat the filtered solution on the substrate. The baking device is configured to bake the solution coated on the substrate. The blowing device is configured to blow an air to the baked solution.

Abstract: A projection device, including an illumination system, a control element, a driving element, a light valve, and a projection lens, is provided. The illumination system includes multiple light sources for providing multiple light beams to be combined into an illumination light beam. The driving element respectively drives the light sources in a first mode or a second mode, so that the light beams have respective luminous brightness, and the driving element is switched from the first mode to the second mode according to a first signal. The control element provides the first signal to the driving element according to an optical state or a time state of the projection device. The light valve is adapted to convert the illumination light beam into an image light beam. The projection lens is adapted to project the image light beam out of the projection device.

Abstract: An integrated circuit device includes a substrate and a memory device. The memory device is over the substrate. The memory device includes a bottom electrode, a dielectric layer, an antiferroelectric layer, and a top electrode. The dielectric layer is over the bottom electrode. The antiferroelectric layer is over the dielectric layer. The top electrode is over the antiferroelectric layer.

Abstract: A method includes forming a semiconductor layer over a substrate; depositing a first ferroelectric layer over a channel region of the semiconductor layer; depositing a first dielectric layer over the first ferroelectric layer; depositing a second ferroelectric layer over the first dielectric layer; depositing a gate metal layer over the second ferroelectric layer; patterning the gate metal layer, the second ferroelectric layer, the first dielectric layer, and the first ferroelectric layer to form a gate structure; and forming source/drain regions in the semiconductor layer and on opposite sides of the gate structure.

Abstract: An intelligent display assembly includes a display and a microcontroller. The display is mounted to a CNC machine and provided with a light emitting module and a display module opposite to the light emitting module. The microcontroller is electrically connected with the CNC machine and the display, such that the microcontroller receives an operating status signal outputted by the CNC machine, and according to the operating status signal, the microcontroller controls the light emitting module to emit light and controls the display module to display processing information, such as processing time, processing quantity, waiting time, and failure time. This allows operators to grasp the processing information in real time and improve management efficiency.

Abstract: A chip on film package is disclosed, including a flexible film and a chip. The flexible film includes a film base, a patterned metal layer includes a plurality of pads and disposed on an upper surface of the film base, and a dummy metal layer covering a lower surface of the film base and capable of dissipating heat of the chip. The dummy metal layer comprises at least one opening exposing the second surface, and at least one of the plurality of pads is located within the at least one opening in a bottom view of the chip on film package. The chip is mounted on the plurality of pads of the patterned metal layer.

Abstract: A chip on film package including a flexible film, a first patterned circuit layer, one or more first chips, a second patterned circuit layer, and one or more second chips. The flexible film includes a first surface and a second surface opposite to the first surface. The first patterned circuit layer is disposed on the first surface. The one or more first chips are mounted on the first surface and electrically connected to the first patterned circuit layer. The second patterned circuit layer is disposed on the second surface. The one or more second chips are mounted on the second surface and electrically connected to the second patterned circuit layer.

Abstract: A display device and a driving device thereof is disclosed. The driving device is coupled to a display panel. The driving device includes at least one first driver integrated circuit (IC) and at least one second driver integrated circuit (IC). The first driver integrated circuit is coupled to the display panel. The first driver integrated circuit drives the display panel and detects a first working temperature. The second driver integrated circuit is coupled to the display panel and the first driver IC. The second driver integrated circuit drives the display panel. The first driver IC stops driving the display panel and communicates with the second driver IC to stop driving the display panel when the first working temperature is substantially higher than a first given temperature.

Abstract: A display device and a driving device thereof is disclosed. The driving device is coupled to a display panel. The driving device includes at least one first driver integrated circuit (IC) and at least one second driver integrated circuit (IC). The first driver integrated circuit is coupled to the display panel. The first driver integrated circuit drives the display panel and detects a first working temperature. The second driver integrated circuit is coupled to the display panel and the first driver IC. The second driver integrated circuit drives the display panel. The first driver IC stops driving the display panel and communicates with the second driver IC to stop driving the display panel when the first working temperature is substantially higher than a first given temperature.

Abstract: A chip on film package is disclosed, including a flexible film and a chip. The flexible film includes a film base, a patterned metal layer includes a plurality of pads and disposed on an upper surface of the film base, and a dummy metal layer covering a lower surface of the film base and capable of dissipating heat of the chip. The dummy metal layer comprises at least one opening exposing the second surface, and at least one of the plurality of pads is located within the at least one opening in a bottom view of the chip on film package. The chip is mounted on the plurality of pads of the patterned metal layer.

Abstract: A chip on film package is disclosed, including a flexible film, a patterned circuit layer, a chip, and a dummy metal layer. The flexible film includes a first surface and a second surface opposite to the first surface. The patterned circuit layer is disposed on the first surface. The chip is mounted on the first surface and electrically connected to the patterned circuit layer. The dummy metal layer covers the second surface capable of dissipating heat of the chip. The dummy metal layer is electrically insulated from the patterned circuit layer.

Abstract: Provided is a memory device including: a memory array, including a flag memory array having a plurality of flag memory cells and a data memory array having a plurality of data memory cells, the corresponding flag memory cells being used to record whether the corresponding data memory cells have been written or not. In initialization, the flag memory array is initialized by the control circuit but the data memory array is not initialized.

Abstract: The embodiment of the present invention discloses a memory device and a method for operating the same. The memory device includes a memory array and a logic circuit. The logic circuit is coupled to the memory array, and is configured to perform a corresponding operation in response to an operation command from a controller. When an interruption event occurs during the corresponding operation, the logic circuit records a memory status, and the logic circuit further is configured to output the memory status to the controller in response to a status read command from the controller.

Abstract: A chip on film package including a flexible film, a first patterned circuit layer, one or more first chips, a second patterned circuit layer, and one or more second chips. The flexible film includes a first surface and a second surface opposite to the first surface. The first patterned circuit layer is disposed on the first surface. The one or more first chips are mounted on the first surface and electrically connected to the first patterned circuit layer. The second patterned circuit layer is disposed on the second surface. The one or more second chips are mounted on the second surface and electrically connected to the second patterned circuit layer.

Abstract: A chip on film package is disclosed, including a flexible film, a patterned circuit layer, a chip, and a dummy metal layer. The flexible film includes a first surface and a second surface opposite to the first surface. The patterned circuit layer is disposed on the first surface. The chip is mounted on the first surface and electrically connected to the patterned circuit layer. The dummy metal layer covers the second surface capable of dissipating heat of the chip. The dummy metal layer is electrically insulated from the patterned circuit layer.

Abstract: A memory device comprises an array of memory cells, and a plurality of sense amplifiers coupled with the memory cells. A controller is configured to execute a read operation in response to a command and address, including a read cycle in which the memory cells at the address are electrically coupled to the sense amplifiers, and in which the memory cells at the address are electrically decoupled from the sense amplifiers in response to a timing signal.

Abstract: A memory device including an array of memory cells including bit lines, and biasing circuitry cells. A sense amplifier has a data line input connected to a data line, and a reference input. The controllable reference current source can be connected to the reference input of the sense amplifier. Control circuits on the device are configured to cause execution of a read operation, where the read operation includes a first phase in which the array is biased to induce leakage current on the selected bit line, and a second phase in which the array is biased to read a selected memory cell on the selected bit line. A circuit on the device is configured to sample the leakage current in the first phase, and to control the controllable reference current source during the second phase, as a function of the sampled leakage current.