Abstract: A method for programming a memory is provided. The memory includes a number of cells and has a preset PV level for a target cell. The method includes programming a first-side of the target cell to have a Vt level not lower than the preset PV level; reading a Vt level of a second-side of the target cell and accordingly obtaining a corrected PV level corresponding to the first-side; and programming the first-side of the target cell to have a Vt level not lower than the corresponding corrected PV level.

Abstract: A memory circuit with relatively high reading speed and relatively low switching noise is provided. The memory circuit includes an output buffer device having a first input receiving a data signal having a first voltage level, a second input receiving a pre-set voltage having a second voltage level and an output outputting the data signal, and a pre-set circuit constructed by a pair of MOSFETs and providing the pre-set voltage to the second input before the output buffer device receives the data signal. The pre-set circuit receives a control signal activating the pair of MOSFETs at the same time, and when the output buffer device receives the data signal, a voltage level of the second input is swung from the second level to the first voltage level.

Abstract: A memory 1-bit error checking method is provided. Firstly, at least one piece of data fragment whose side is 2n bits is received. Next, an error correction code, a parity code and a data code are generated and written in the memory. Then, the at least one piece of data fragment is read from the memory and used as at least one piece of read data fragment. Next, a new error correction code, a new parity code and a new data code are generated. Afterwards, a determination as to whether the at least one piece of read data fragment has a 1-bit error is made. After that, if the at least one piece of read data fragment does not have a 1-bit error, then the at least one piece of read data fragment is outputted.

Abstract: A memory structure is provided. The memory structure includes a memory array, an error correct code (ECC) unit, and a comparator. The memory array includes at least one memory cell being written and storing at least one original data. The ECC unit is for reading at least one tested data from the at least one memory cell, correcting the at least one tested data when there is an error occurred in the at least one tested data and outputting at least one ECC data accordingly. The comparator is for determining whether the at least one original data is substantially the same as the at least one ECC data or not and outputting an output signal indicating whether the at least one memory cell passes or fails.

Abstract: A low voltage complementary metal oxide semiconductor (CMOS) process tri-state buffer includes a logic device, a biasing device and a switch device. The logic device receives an input signal and an enable signal and generates a first control signal and a second control signal. The biasing device receives the first control signal and thus controls a voltage level of a third control signal. The switch device receives the second and third control signals and respectively couples an output terminal to a first external voltage source and a second external voltage source when the second and third control signals are enabled. When the enable signal is disabled, the second and third control signals are simultaneously disabled so that the output terminal is floating with respect to the first and second external voltage sources and the output terminal is held in a high impedance state.

Abstract: A verification process is disclosed for verifying correctness of a data status of a flash memory after data of the flash memory is altered. The flash memory has a plurality of memory cells array and a volatile memory. The verification process includes reading memory-cell verification data stored in the volatile memory, wherein the memory-cell verification data is for indicating a previous verification result of each memory cell is ‘success’ or ‘failure’; and performing a verification procedure on the memory cells failed in previous verification according to the memory-cell verification data, but not on the remained memory cells successful in previous verification.

Abstract: A low voltage complementary metal oxide semiconductor (CMOS) process tri-state buffer includes a logic device, a biasing device and a switch device. The logic device receives an input signal and an enable signal and generates a first control signal and a second control signal. The biasing device receives the first control signal and thus controls a voltage level of a third control signal. The switch device receives the second and third control signals and respectively couples an output terminal to a first external voltage source and a second external voltage source when the second and third control signals are enabled. When the enable signal is disabled, the second and third control signals are simultaneously disabled so that the output terminal is floating with respect to the first and second external voltage sources and the output terminal is held in a high impedance state.

Abstract: The driving circuit and system of the present invention for driving an organic thin-film EL element to luminesce can speed up the overall display speed by pre-charging the organic thin-film EL element. Since the present invention improves the non-linear distortion in the prior art during signal switching, a more precise value can be obtained on calculating the rang for gray-level display. The present invention can correctly input a data signal with a pulse width proportional to the gray-level to be displayed on the organic thin-film EL element.