Abstract: A memory device including an array of memory cells including bit lines, and biasing circuitry cells. A sense amplifier has a data line input connected to a data line, and a reference input. The controllable reference current source can be connected to the reference input of the sense amplifier. Control circuits on the device are configured to cause execution of a read operation, where the read operation includes a first phase in which the array is biased to induce leakage current on the selected bit line, and a second phase in which the array is biased to read a selected memory cell on the selected bit line. A circuit on the device is configured to sample the leakage current in the first phase, and to control the controllable reference current source during the second phase, as a function of the sampled leakage current.

Abstract: A memory device including an array of memory cells including bit lines, and biasing circuitry cells. A sense amplifier has a data line input connected to a data line, and a reference input. The controllable reference current source can be connected to the reference input of the sense amplifier. Control circuits on the device are configured to cause execution of a read operation, where the read operation includes a first phase in which the array is biased to induce leakage current on the selected bit line, and a second phase in which the array is biased to read a selected memory cell on the selected bit line. A circuit on the device is configured to sample the leakage current in the first phase, and to control the controllable reference current source during the second phase, as a function of the sampled leakage current.

Abstract: Provided is a memory device including: a memory array, including a flag memory array having a plurality of flag memory cells and a data memory array having a plurality of data memory cells, the corresponding flag memory cells being used to record whether the corresponding data memory cells have been written or not. In initialization, the flag memory array is initialized by the control circuit but the data memory array is not initialized.

Abstract: A memory device includes command logic allowing for a command protocol allowing interruption of a first command sequence, such as a page write sequence, and then to proceed directly to receive and decode a second command sequence, such as a read sequence, without latency associated, completing the first command sequence. Also, the command logic is configured to be responsive to a third command sequence after the second command sequence and its associated embedded operation have been completed, which completes the interrupted first command sequence and enables execution of an embedded operation identified by the first command sequence. A memory controller supporting such protocols is described.

Abstract: The embodiment of the present invention discloses a memory device and a method for operating the same. The memory device includes a memory array and a logic circuit. The logic circuit is coupled to the memory array, and is configured to perform a corresponding operation in response to an operation command from a controller. When an interruption event occurs during the corresponding operation, the logic circuit records a memory status, and the logic circuit further is configured to output the memory status to the controller in response to a status read command from the controller.

Abstract: A row decoder includes a plurality of address lines, a first selection circuit and a second selection circuit. The first selection circuit is coupled to the address lines and with a latch function, and configured to enable and latch a first selection signal to select a first word line in a first cell array. The second selection circuit is coupled to the address lines and without the latch function, and configured to enable a second selection signal to select a second word line in a second cell array.

Abstract: A light adjusting sheet includes a base and a first light adjusting structure layer. The base includes a first surface and a second surface opposite to the first surface. The first light adjusting structure layer is disposed on the first surface of the base, and the first light adjusting structure layer includes a plurality of light adjusting structures. Each light adjusting structure includes a major axis, a minor axis and a thickness, wherein the major axis of the light adjusting structure is in parallel with an extending direction. A ratio of a length of the minor axis to a length of the major axis is between 0.093 and 0.6, and the thickness is between 2 ?m to 6 ?m. A backlight module using the light adjusting sheet can achieve high brightness and large viewing angle.

Abstract: A memory device includes command logic allowing for a command protocol allowing interruption of a first command sequence, such as a page write sequence, and then to proceed directly to receive and decode a second command sequence, such as a read sequence, without latency associated, completing the first command sequence. Also, the command logic is configured to be responsive to a third command sequence after the second command sequence and its associated embedded operation have been completed, which completes the interrupted first command sequence and enables execution of an embedded operation identified by the first command sequence. A memory controller supporting such protocols is described.

Abstract: A polishing machine is disclosed to include a machine body and a carrier movably coupled to the machine body. A polishing device is provided with a movable base movably coupled to the machine body and a plurality of polishing cylinders rotatably connected to the movable base and located above the carrier. A rotary drive device is provided with a plurality of transmission gears each coupled to one of the polishing cylinders, and two rotary drive motors symmetrically mounted to the movable base and each having a gear shaft for driving the transmission gears to rotate through at least one transmission belt. Thus, the polishing cylinders are moved along with the movable base and rotated by the actuation of the rotary drive motors for smoothing the workpieces placed on the carrier.

Abstract: A light adjusting sheet includes a base and a first light adjusting structure layer. The base includes a first surface and a second surface opposite to the first surface. The first light adjusting structure layer is disposed on the first surface of the base, and the first light adjusting structure layer includes a plurality of light adjusting structures. Each light adjusting structure includes a major axis, a minor axis and a thickness, wherein the major axis of the light adjusting structure is in parallel with an extending direction. A ratio of a length of the minor axis to a length of the major axis is between 0.093 and 0.6, and the thickness is between 2 mm to 6 mm. A backlight module using the light adjusting sheet can achieve high brightness and large viewing angle.

Abstract: A memory includes a local word line driver for a memory array having a first word line and a second word line. The local word line driver includes a first selection transistor, a second selection transistor, and a middle transistor disposed between the first and second selection transistors. The first word line couples to the first selection transistor and the middle transistor, and the second word line couples to the middle transistor and the second selection transistor.

Abstract: An operation method for a memory is provided. The operation method includes: starting a power on procedure on the memory; checking leakage for a bit line of the memory; and if the bit line has leakage, performing a leakage recovery on the bit line until the bit line passes the checking leakage step.

Abstract: A method for programming a memory is provided. The memory includes a number of cells and has a preset PV level for a target cell. The method includes programming a first-side of the target cell to have a Vt level not lower than the preset PV level; reading a Vt level of a second-side of the target cell and accordingly obtaining a corrected PV level corresponding to the first-side; and programming the first-side of the target cell to have a Vt level not lower than the corresponding corrected PV level.

Abstract: An operation method for a memory is provided. The operation method includes: starting a power on procedure on the memory; checking leakage for a bit line of the memory; and if the bit line has leakage, performing a leakage recovery on the bit line until the bit line passes the checking leakage step.

Abstract: A memory includes a local word line driver for a memory array having a first word line and a second word line. The local word line driver includes a first selection transistor, a second selection transistor, and a middle transistor disposed between the first and second selection transistors. The first word line couples to the first selection transistor and the middle transistor, and the second word line couples to the middle transistor and the second selection transistor.

Abstract: A fluorescence detection system for measuring biomolecules is disclosed, which includes a fluorescence detection device, a light source, a sample-loading unit, and an analysis-reading device. The fluorescence detection device has a substrate and plural phototransistors arranged on the substrate, and each phototransistor contains an emitter, a collector locating on the substrate, and a base between the emitter and the collector. The base-collector diode junction functions as an absorber to convert fluorescence to photocurrent. The light source serves to excite a fluorescent dye contained in a biomolecule sample. The sample-loading unit is used to load or transport the excited biomolecule sample onto a sensing zone of the fluorescence detection device. The analysis-reading device is to measure photocurrent output from the fluorescence detection device under a bias. Hence, the biomolecule content can be easily determined by the fluorescence detection system.

Abstract: A memory circuit with relatively high reading speed and relatively low switching noise is provided. The memory circuit includes an output buffer device having a first input receiving a data signal having a first voltage level, a second input receiving a pre-set voltage having a second voltage level and an output outputting the data signal, and a pre-set circuit constructed by a pair of MOSFETs and providing the pre-set voltage to the second input before the output buffer device receives the data signal. The pre-set circuit receives a control signal activating the pair of MOSFETs at the same time, and when the output buffer device receives the data signal, a voltage level of the second input is swung from the second level to the first voltage level.

Abstract: A method for programming a memory is provided. The memory includes multiple rows of memory cells each including two half cells. The method includes the following steps. Whether the two half cells of a to-be-programmed memory cell of the nth row memory cells are both needed to be programmed or not is determined, wherein n is a positive integer. If the two half cells of the to-be-programmed memory cell are both needed to be programmed, a first initial programming bias voltage corresponding to the nth row memory cells is applied to program the to-be-programmed memory cell. Otherwise, a second initial programming bias voltage corresponding to the nth row memory cells is applied to program the to-be-programmed memory cell. The second initial programming bias voltage is higher than the first initial programming bias voltage.

Abstract: A memory 1-bit error checking method is provided. Firstly, at least one piece of data fragment whose side is 2n bits is received. Next, an error correction code, a parity code and a data code are generated and written in the memory. Then, the at least one piece of data fragment is read from the memory and used as at least one piece of read data fragment. Next, a new error correction code, a new parity code and a new data code are generated. Afterwards, a determination as to whether the at least one piece of read data fragment has a 1-bit error is made. After that, if the at least one piece of read data fragment does not have a 1-bit error, then the at least one piece of read data fragment is outputted.

Abstract: A method for programming a memory is provided. The memory includes multiple rows of memory cells each including two half cells. The method includes the following steps. Whether the two half cells of a to-be-programmed memory cell of the nth row memory cells are both needed to be programmed or not is determined, wherein n is a positive integer. If the two half cells of the to-be-programmed memory cell are both needed to be programmed, a first initial programming bias voltage corresponding to the nth row memory cells is applied to program the to-be-programmed memory cell. Otherwise, a second initial programming bias voltage corresponding to the nth row memory cells is applied to program the to-be-programmed memory cell. The second initial programming bias voltage is higher than the first initial programming bias voltage.