Patents by Inventor Chun-An Huang

Chun-An Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240188866
    Abstract: An early assistive diagnosis system of ADHD provides a test to the subject and uses a brain-computer interface (BCI) to detect the electroencephalography (EEG) signals of subject. A host receives the EEG signals, captures the features associated with ADHD heterogeneities, obtains feature EEG signals, and classifies the subject as typical development or ADHD, then uses the EEG feature signals to train a predicted index score range for the heterogeneities of ADHD. The test scores of a new subject is tested, it is compared whether the scores fall within the predicted index score range to determine the ADHD heterogeneity types to which the new subject belongs. Thus, the present invention uses attention tests for ADHD in combination with EEG signals to assess symptoms of a subject, further predicts the potential aptitude of a subject for ADHD and provides objective assistive diagnosis to physicians.
    Type: Application
    Filed: December 7, 2023
    Publication date: June 13, 2024
    Applicant: National Yang Ming Chiao Tung University
    Inventors: Li-Wei KO, I-Chun CHEN, I-Wen HUANG, Jo-Wei LIN, Zuo-Cian FAN, Chih-Hao CHANG, Yang CHANG
  • Publication number: 20240194692
    Abstract: A display panel includes a substrate, first, second, and third data lines, scan lines, a first active device, a second active device, and pixel electrodes. The first and the third data lines have a first polarity. The second data line has a second polarity. The first polarity is different from the second polarity. A source electrode of the first active device disposed between the first data line and the second data line is electrically connected to the first data line. An extension region of the semiconductor pattern of the first active device extends toward and overlaps the second data line. A source electrode of the second active device disposed between the second data line and the third data line is electrically connected to the second data line. An extension region of the semiconductor pattern of the second active device extends toward and overlaps the third data line.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 13, 2024
    Applicant: AUO Corporation
    Inventors: Hsiu-Chun Hsieh, Shu-Hui Huang, Yi-Wei Chen
  • Publication number: 20240194591
    Abstract: A package structure includes a thermal dissipation structure including a substrate, a first encapsulant laterally covering the substrate, a die disposed on the substrate and including a sensing region, a second encapsulant laterally covering the die, and a redistribution structure disposed on the die and the second encapsulant. An outer sidewall of the second encapsulant is laterally offset from an outer sidewall of the first encapsulant. The die is electrically coupled to the substrate through the redistribution structure, and the redistribution structure includes a hollow region overlying the sensing region of the die.
    Type: Application
    Filed: February 20, 2024
    Publication date: June 13, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Patent number: 12010549
    Abstract: In 5GS, Single-Network Slice Selection Assistance Information (S-NSSAI) based backoff (BO) timers (T3584/T3585) can be applied to either the registered PLMN or all the PLMNs based on a 5GSM congestion re-attempt indicator. For a specific PDU session, the corresponding BO timer applied to the registered PLMN and the BO timer applied to all PLMN can be both running concurrently. It is proposed for a UE to stop both the BO timer applied to all the PLMNs and the BO timer applied to the registered PLMN, if running, in all the following scenarios: 1) Receiving a PDU session release command without a BO timer, 2) Receiving a PDU session release command with 5GSM cause #39, 3) Receiving a PDU session modification command, 4) Receiving a 5GSM message with a 5GSM congestion control BO timer value, and 5) Receiving a PDU session authentication command.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: June 11, 2024
    Inventors: Chien-Chun Huang-Fu, Bo-Hun Chen, Chi-Hsien Chen, Shang-Ru Mo
  • Patent number: 12010298
    Abstract: An example device for decoding video data includes memory configured to store the video data and one or more processors implemented in circuitry and communicatively coupled to the memory. The one or more processors are configured to reshape a pixel domain reference template block using a forward mapping function into a mapped domain reference template block and derive local illumination compensation (LIC) model parameters from the mapped domain reference template block and a mapped domain neighboring reconstruction template block. The one or more processors are configured to apply the LIC model parameters to motion-compensated prediction signals and decode the video data based on the application of the LIC model parameters.
    Type: Grant
    Filed: May 30, 2023
    Date of Patent: June 11, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Chun-Chi Chen, Han Huang, Vadim Seregin, Marta Karczewicz
  • Patent number: 12010552
    Abstract: A method for 5G Session Management (5GSM) handling of network rejection not due to congestion control is provided. A User Equipment (UE) receives a 5GSM reject message from a mobile communication network. The 5GSM reject message indicates a network rejection not due to congestion control. The UE associates a back-off timer with a Home Public Land Mobile Network (HPLMN) Single-Network Slice Selection Assistance Information (S-NSSAI). The UE prevents itself from sending a 5GSM request message for the same HPLMN S-NSSAI that is associated with the back-off timer.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: June 11, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chien-Chun Huang-Fu, Bo-Hun Chen
  • Patent number: 12009033
    Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: June 11, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chen-Ming Huang, Wen-Tuo Huang, Yu-Hsiang Yang, Yu-Ling Hsu, Wei-Lin Chang, Chia-Sheng Lin, ShihKuang Yang, Yu-Chun Chang, Hung-Ling Shih, Po-Wei Liu, Shih-Hsien Chen
  • Patent number: 12002768
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution structure, and conductive vias. The molded semiconductor device comprises a sensor die with a first surface and a second surface opposite the first surface, wherein the sensor die has an input/output region and a sensing region at the first surface. The first redistribution structure is disposed on the first surface of the sensor die, wherein the first redistribution structure covers the input/output region and exposes the sensing region, and the first redistribution structure comprises a conductive layer having a redistribution pattern and a ring structure. The redistribution pattern is electrically connected with the sensor die. The ring structure surrounds the sensing region and is separated from the redistribution pattern, wherein the ring structure is closer to the sensing region than the redistribution pattern.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: June 4, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Huang, Chih-Hao Chang, Po-Chun Lin, Chun-Ti Lu, Zheng-Gang Tsai, Shih-Wei Chen, Chia-Hung Liu, Hao-Yi Tsai, Chung-Shi Liu
  • Publication number: 20240178052
    Abstract: A semiconductor structure includes a substrate, a first gate structure and a second gate structure disposed over the substrate, and an isolation feature extending through the substrate and disposed between the first gate structure and the second gate structure. A top surface of the isolation feature is above a topmost surface of the first gate structure.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Inventors: Wang-Chun HUANG, Yu-Xuan HUANG, Hou-Yu CHEN, Chih-Hao WANG, Kuan-Lun CHENG
  • Publication number: 20240178748
    Abstract: A power apparatus includes a substrate, a first power circuit, and a second power circuit. The substrate includes a first metallization region, a second metallization region, and a third metallization region which are separated from each other. The first power circuit is electrically connected to the first metallization region and the third metallization region, and is arranged across the second metallization region and fails to be in contact with the second metallization region. The second power circuit is electrically connected to the second metallization region and the third metallization region, and fails to be in contact with the first metallization region.
    Type: Application
    Filed: November 20, 2023
    Publication date: May 30, 2024
    Inventors: Jason HUANG, Liang-Yo CHEN, Pi-Sheng HSU, Chun-Ming WEI
  • Publication number: 20240178120
    Abstract: An integrated fan-out package includes a first redistribution structure, a die, conductive structures, an encapsulant, and a second redistribution structure. The first redistribution structure has first regions and a second region surrounding the first regions. A metal density in the first regions is smaller than a metal density in the second region. The die is disposed over the first redistribution structure. The conductive structures are disposed on the first redistribution structure to surround the die. Vertical projections of the conductive structures onto the first redistribution structure fall within the first regions of the first redistribution structure. The encapsulant encapsulates the die and the conductive structures. The second redistribution structure is disposed on the encapsulant, the die, and the conductive structures.
    Type: Application
    Filed: February 8, 2023
    Publication date: May 30, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Tzu-Sung Huang, Wei-Kang Hsieh, Hao-Yi Tsai, Ming-Hung Tseng, Tsung-Hsien Chiang, Yen-Liang Lin, Chu-Chun Chueh
  • Publication number: 20240175104
    Abstract: A method of preparing scandium metal includes mixing aluminum powder and scandium fluoride powder to form a mixture, heating the mixture in a vacuum environment to react the aluminum powder with the scandium fluoride powder for forming aluminum fluoride gas and scandium metal, and removing the aluminum fluoride gas by evacuation to obtain the scandium metal.
    Type: Application
    Filed: November 29, 2022
    Publication date: May 30, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Sheng-Chun FU, Yang-Sheng HUANG, Chia-Ming CHANG
  • Publication number: 20240175810
    Abstract: A gas sensing device for detecting a to-be-detected substance in a respiratory gas exhaled by a user includes a housing permitting entrance of the respiratory gas, and a sensing module disposed in the housing. The sensing module includes a light chamber permitting the respiratory gas to pass therethrough, a light source unit emitting light into the light chamber, first and second light sensing units outputting respectively first and second detected signals indicating first and second detected intensities respectively of first and second portions of the light whose wavelengths fall within first and second wavelength ranges, respectively, and a processing unit electrically connected to the first and second light sensing units and determining, based on the first and second detected signals, that the to-be-detected substance exists in the respiratory gas when a difference occurs in each of the first and second detected intensities over time.
    Type: Application
    Filed: May 17, 2023
    Publication date: May 30, 2024
    Inventors: Yu-Ren HUANG, Li-Yu WANG, Ming-Chun HSIAO, Chun-Han HUANG, Yu-Da CHIU
  • Publication number: 20240168057
    Abstract: A probe card for high-frequency testing is provided. The probe card includes a substrate, a flexible substrate, a probe, and at least one movable conductive pillar. The substrate has a first surface, a second surface, and at least one first through hole. The flexible substrate is disposed on the second surface of the substrate and has at least one second through hole. The second through hole and the first through hole correspond to each other. The probe is disposed on the second surface of the substrate, and is electrically connected to the flexible substrate. The movable conductive pillar movably passes through the first through hole and the second through hole.
    Type: Application
    Filed: April 10, 2023
    Publication date: May 23, 2024
    Inventors: HUNG-CHUN HUANG, WEN-HAO CHENG, YUAN-TING TAI
  • Publication number: 20240170537
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. In addition, the nanostructures includes channel regions and source/drain regions. The semiconductor structure further includes a gate structure vertically sandwiched the channel regions of the nanostructures and a contact wrapping around and vertically sandwiched between the source/drain regions of the nanostructures.
    Type: Application
    Filed: February 1, 2024
    Publication date: May 23, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Kuo-Hua PAN, Jhon-Jhy LIAW, Chao-Ching CHENG, Hung-Li CHIANG, Shih-Syuan HUANG, Tzu-Chiang CHEN, I-Sheng CHEN, Sai-Hooi YEONG
  • Publication number: 20240170364
    Abstract: A semiconductor device package and a method of manufacturing a semiconductor device package are provided. The semiconductor device package includes at least one electronic component, a heat source, and a heat dissipation element. The heat source is adjacent to the electronic component. The heat dissipation element is disposed adjacent to the heat source and the electronic component. The heat dissipation element includes a heat transmitting structure configured to reduce heat, which is from the heat source, through the heat dissipation element, and transmitting in a direction toward the electronic component.
    Type: Application
    Filed: November 23, 2022
    Publication date: May 23, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hung-Hsien HUANG, Wen Chun WU, Chih-Pin HUNG
  • Publication number: 20240158458
    Abstract: The disclosure features lipid nanoparticle (LNP) compositions comprising immune modulating polypeptides and uses thereof. The LNP compositions of the present disclosure comprise mRNA therapeutics encoding immune modulating polypeptides, e.g., interleukin 2 (IL-2) and/or granulocyte macrophage colony stimulating factor (GM-CSF). The LNP compositions of the present disclosure can stimulate T regulatory cells, e.g., increase the level and/or activity of T regulatory cells in vivo or ex vivo.
    Type: Application
    Filed: October 15, 2020
    Publication date: May 16, 2024
    Inventors: Eric Yi-Chun Huang, Jared Iacovelli, Seymour De Picciotto, Sze-Wah Tse, Laurie Kenney
  • Publication number: 20240158992
    Abstract: A pulp-molding mould assembly with a heating device is configured for integrally forming paper-made articles, and comprises: at least one mould and a number of heating tubes. The at least one mould has a main accommodating chamber which is defined with a main three-dimensional inner circumferential surface and a main inner space. The heating tubes are layer-by-layer arranged into multilayer-stacked structure in an evenly and annularly heating distribution around the main three-dimensional inner circumferential surface. This could not only make the heating tubes evenly heating against the main three-dimensional inner circumferential surface and reduce heat-conducting distances from the heating tubes to the respective paper-made article, for reducing a power consumption thereof, but also make the heating tubes evenly heating an air inside the main inner space for making the main accommodating chamber yields a thermal preservation effect by way of a vacuum heat-insulation thereof.
    Type: Application
    Filed: October 22, 2023
    Publication date: May 16, 2024
    Inventors: CHIEN-KUAN KUO, CHUN-HUANG HUANG
  • Publication number: 20240156092
    Abstract: The invention relates to a composition for promoting the growth of legumes. The composition includes auxin, choline chloride and ?-aminobutyric acid (GABA). The invention also relates to a method for promoting the growth of legumes.
    Type: Application
    Filed: October 26, 2022
    Publication date: May 16, 2024
    Inventors: Ting-Wen CHENG, Cho-Chun HUANG, Gui-Jun Li, Kai XIA, Chen-Pang WU
  • Patent number: D1027976
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: May 21, 2024
    Assignee: VIVOTEK INC.
    Inventors: Kuan-Hung Chen, Kai-Sheng Chuang, Chia-Chi Chang, Yu-Fang Huang, Kai-Ting Yu, Wen-Chun Chen, Shu-Jung Hsu, Tsao-Wei Hung