Abstract: A method of manufacturing a semiconductor device includes forming a fin structure including a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, forming an isolation insulating layer so that the hard mask layer and the stacked layer are exposed from the isolation insulating layer, forming a sacrificial cladding layer over at least sidewalls of the exposed hard mask layer and stacked layer, forming layers of a first dielectric layer and an insertion layer over the sacrificial cladding layer and the fin structure, performing an annealing operation to convert a portion of the layers of the first dielectric layer and the insertion layer from an amorphous form to a crystalline form, and removing the remaining amorphous portion of the layers of the first dielectric layer and the insertion layer to form a recess.

Abstract: A method includes providing a semiconductor substrate having a first region and a second region, epitaxially growing a semiconductor layer above the semiconductor substrate, patterning the semiconductor layer to form a first fin in the first region and a second fin in the second region, and depositing a dielectric material layer on sidewalls of the first and second fins. The method also includes performing an anneal process in driving dopants into the dielectric material layer, such that a dopant concentration in the dielectric material layer in the first region is higher than that in the second region, and performing an etching process to recess the dielectric material layer, thereby exposing the sidewalls of the first and second fins. A top surface of the recessed dielectric material layer in the first region is lower than that in the second region.

Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.

Abstract: An apparatus, method, and system for determining body wave slowness from guided borehole waves. The method includes selecting a target axial resolution based on the size of a receiver array, obtaining a plurality of waveform data sets corresponding to a target formation zone and each acquired at a different shot position, computing a slowness-frequency 2D dispersion semblance map for each waveform data set, stacking the slowness-frequency 2D dispersion semblance maps to generate a stacked 2D semblance map, and determining a body wave slowness from the extracted dispersion curve. The method may also include generating a self-adaptive weighting function based on a dispersion model and the extracted dispersion curve, fitting the weighted dispersion curve and the dispersion model to determine a body wave slowness that minimizes the misfit between the weighted dispersion curve and the dispersion model. The method can be applied to both frequency-domain and time-domain processing.

Abstract: A power monitor includes a detecting circuit, a processing circuit, and a warning circuit. The detecting circuit detects a first abnormal condition of a primary side circuit and a second abnormal condition of a secondary side circuit. The processing circuit calculates a first class and a first occurring number of the first abnormal condition, and calculates a second class and a second occurring number of the second abnormal condition. The processing circuit determines whether the first occurring number is larger than a first predetermined number corresponding to the first class; if it is, the processing circuit outputs a first abnormal signal. The processing circuit determines whether the second occurring number is larger than a second predetermined number corresponding to the second class; if it is, the processing circuit outputs a second abnormal signal. The warning circuit outputs a warning signal according to the first or the second abnormal signal.

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a dielectric material structure having a trench therein. A conductive interconnect line in the trench, the conductive interconnect line having a length and a width, the width having a cross-sectional profile, wherein the cross-sectional profile of the width of the conductive interconnect line has a bottom lateral width, a mid-height lateral width, and a top lateral width, and wherein the mid-height lateral width is greater than the bottom lateral width, and the mid-height lateral width is greater than the top lateral width.

Abstract: Semiconductor structures and methods of forming the same are provided. A method according to the present disclosure includes forming a stack of epitaxial layers over a substrate, forming a first fin-like structure and a second fin-like structure from the stack, forming an isolation feature between the first fin-like structure and the second fin-like structure, forming a cladding layer over the first fin-like structure and the second fin-like structure, conformally depositing a first dielectric layer over the cladding layer, depositing a second dielectric layer over the first dielectric layer, planarizing the first dielectric layer and the second dielectric layer until the cladding layer are exposed, performing an etch process to etch the second dielectric layer to form a helmet recess, performing a trimming process to trim the first dielectric layer to widen the helmet recess, and depositing a helmet feature in the widened helmet recess.

Abstract: Techniques for improved extreme ultraviolet (EUV) patterning using assist features, related transistor structures, integrated circuits, and systems, are disclosed. A number of semiconductor fins and assist features are patterned into a semiconductor substrate using EUV. The assist features increase coverage of absorber material in the EUV mask, thereby reducing bright field defects in the EUV patterning. The semiconductor fins and assist features are buried in fill material and a mask is patterned that exposes the assist features and covers the semiconductor fins. The exposed assist features are partially removed and the protected active fins are ultimately used in transistor devices.

Abstract: A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.

Abstract: A semiconductor device includes a substrate, a plurality of insulators, a liner structure and a gate stack. The substrate has fins and trenches in between the fins. The insulators are disposed within the trenches of the substrate. The liner structure is disposed on the plurality of insulators and across the fins, wherein the liner structure comprises sidewall portions and a cap portion, the sidewall portions is covering sidewalls of the fins, the cap portion is covering a top surface of the fins and joined with the sidewall portions, and a maximum thickness T1 of the cap portion is greater than a thickness T2 of the sidewall portions. The gate stack is disposed on the liner structure and across the fins.

Abstract: Semiconductor structures and methods of forming the same are provided. A method according to the present disclosure includes forming a stack of epitaxial layers over a substrate, forming a first fin-like structure and a second fin-like structure from the stack, forming an isolation feature between the first fin-like structure and the second fin-like structure, forming a cladding layer over the first fin-like structure and the second fin-like structure, conformally depositing a first dielectric layer over the cladding layer, depositing a second dielectric layer over the first dielectric layer, planarizing the first dielectric layer and the second dielectric layer until the cladding layer are exposed, performing an etch process to etch the second dielectric layer to form a helmet recess, performing a trimming process to trim the first dielectric layer to widen the helmet recess, and depositing a helmet feature in the widened helmet recess.

Abstract: Fin cuts in neighboring gate and source or drain regions for advanced integrated circuit structure fabrication is described. For example, an integrated circuit structure includes a horizontal stack of semiconductor nanowire portions. A dielectric gate spacer is vertically over the horizontal stack of semiconductor nanowire portions. A gate isolation structure is laterally adjacent to a first side of the horizontal stack of semiconductor nanowire portions. A source or drain isolation structure is laterally adjacent to a second side of the horizontal stack of semiconductor nanowire portions.

Abstract: Spacer self-aligned via structures for gate contact or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers protrudes above the plurality of gate structures and above the plurality of conductive trench contact structures. A conductive structure is in direct contact with one of the plurality of gate structures or with one of the plurality of conductive trench contact structures.

Abstract: Gate aligned fin cut for advanced integrated circuit structure fabrication is described. For example, an integrated circuit structure includes a first fin segment having a fin end, and a second fin segment spaced apart from the first fin segment, the second fin segment having a fin end facing the fin end of the first fin segment. A first gate structure is over the first fin segment, the first gate structure substantially vertically aligned with the fin end of the first fin segment. A second gate structure is over the second fin segment, the second gate structure substantially vertically aligned with the fin end of the second fin segment. An isolation structure is laterally between the fin end of the first fin segment and the fin end of the second fin segment.

Abstract: A method and system method for determining motion of a downhole tool and feeding back drilling performance. The method may comprise taking a synchronous tool face measurement of the downhole tool, taking a synchronous pulse-echo acquisition to estimate a shape of a borehole, inputting at least the shape of the borehole, the center trajectory of the downhole tool, the rotational time of the downhole tool, the position of the downhole tool, and the one or more measurements of the downhole tool into an information fusion for drilling dynamics, identifying at least one of a whirl, a vibration, or a stick-slip of the downhole tool, and identifying one or more borehole condition and a drilling efficiency. A system may comprise a downhole tool, at least two transducers, and an information handling system.

Abstract: Provided is an electronic lock featuring foolproofness and repositionability, including: a lock body, which is formed with teeth and a receiving cavity; a repositionable plate, which is formed with an elongated hole, a perforated portion, and a projecting spot, and is formed, on an underside thereof, with teeth, such that the teeth of the underside of the repositionable plate and the teeth of the lock body are mutually engageable with each other and the elongated hole of the repositionable plate is fixable to the receiving cavity of the lock body by a fastening element, and an escutcheon, which is formed with a fixing hole and a foolproof hole, such that the escutcheon is fit, by means of the foolproof hole, to the projecting spot of the repositionable plate and the escutcheon is fixed to the perforated portion of the repositionable plate by a fastening element.

Abstract: A method for evaluating a sealing material positioned between a casing of a wellbore and a subsurface formation in which the wellbore is formed includes emitting an acoustic waveform outward from a position within the casing and detecting a return waveform that is generated in response to the acoustic waveform interacting with a region of interest that includes at least a portion of the sealing material. The method includes determining a first time window of the return waveform associated with the region of interest and trimming the return waveform based on the first time window. The method further includes determining a first spectral power density for the first time window of the trimmed return waveform and determining a composition ratio for the region of interest based on the first spectral power density.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: A logging-while-drilling (LWD) tool for use within a formation. The LWD tool may include a transmitter, a receiver, and an acoustic isolator. The transmitter may be operable to transmit an acoustic signal into the formation. The receiver may be operable to receive an acoustic response from the formation. The acoustic isolator may be positioned longitudinally between the transmitter and the receiver to reduce a transfer of acoustic energy between the transmitter and the receiver through the LWD tool. The acoustic isolator may include annular chambers formed in a body of the acoustic isolator and positioned along a longitudinal axis of the acoustic isolator.

Abstract: Methods, systems, and program products are disclosed for implementing acoustic logging and determining wellbore material characteristics. In some embodiments, a method may include determining a polar differential signal for each of one or more pairs of azimuthally offset acoustic measurements within a wellbore. A reference azimuth is identified based, at least in part, on comparing the polar differential signals to a modeled bonding differential signal within a target response window. The method further includes determining differences between an acoustic measurement at the reference azimuth and acoustic measurements at one or more other azimuths and determining a wellbore material condition based, at least in part, on the determined differences.