Abstract: A system comprises: a filter for removing at least one of a contaminant or gas bubbles from a liquid photoresist to provide a filtered photoresist at an outlet of the filter. The filter has a filter vent. A trap has an inlet coupled to receive the filtered photoresist from the filter, for removing a remaining contaminant or gas bubbles from the filtered photoresist. One or more valves and one or more conduits are connected to the filter and the trap. The one or more valves are operable to reverse a direction of flow of the filtered photoresist, so that the photoresist flows from the inlet of the trap, through the outlet of the filter, to the filter vent.

Abstract: A method for pre-treating a wafer surface before applying a material thereon. The method includes positioning the wafer on a rotating apparatus. The wafer is rotated at a first rotational speed between about 50 revolutions per minute (rpm) and about 300 rpm and for a period of about 1 second to about 10 seconds while dispensing a cleaning solvent on the wafer surface. The wafer is rotated at a second rotational speed between about 500 rpm and about 1,500 rpm for a period of about 1 second to about 10 seconds. The wafer is then rotated at a third rotational speed between about 50 rpm and about 300 rpm for a period of about 1 second to about 5 seconds. With the wafer rotating at the third rotational speed, a solvent-containing material is thereafter deposited on the surface of the wafer.

Abstract: The present disclosure provides a developing unit that includes a wafer stage designed to secure a semiconductor wafer; an exhaust mechanism configured around the wafer stage and designed to exhaust a fluid from the semiconductor wafer; and a multi-switch integrated with the exhaust mechanism and designed to control the exhaust mechanism at various open states.

Abstract: A system comprises: a filter for removing at least one of a contaminant or gas bubbles from a liquid photoresist to provide a filtered photoresist at an outlet of the filter. The filter has a filter vent. A trap has an inlet coupled to receive the filtered photoresist from the filter, for removing a remaining contaminant or gas bubbles from the filtered photoresist. One or more valves and one or more conduits are connected to the filter and the trap. The one or more valves are operable to reverse a direction of flow of the filtered photoresist, so that the photoresist flows from the inlet of the trap, through the outlet of the filter, to the filter vent.

Abstract: A method for pre-treating a wafer surface before applying a material thereon. The method includes positioning the wafer on a rotating apparatus. The wafer is rotated at a first rotational speed between about 50 revolutions per minute (rpm) and about 300 rpm and for a period of about 1 second to about 10 seconds while dispensing a cleaning solvent on the wafer surface. The wafer is rotated at a second rotational speed between about 500 rpm and about 1,500 rpm for a period of about 1 second to about 10 seconds. The wafer is then rotated at a third rotational speed between about 50 rpm and about 300 rpm for a period of about 1 second to about 5 seconds. With the wafer rotating at the third rotational speed, a solvent-containing material is thereafter deposited on the surface of the wafer.

Abstract: Substrate for electrical devices is disclosed. An embodiment for the substrate comprised of an insulator, a conductive element(s) and a conductive material(s), wherein the conductive element embedded in the insulator, and two surfaces of the conductive element exposed to two surfaces of the insulator for electrical connection respectively, wherein the upper surface of conductive element is below the upper surface of insulator and is plated by the conductive material, meanwhile the conductive element include a protruding portion which is protruded the insulator, in this manner, solder balls are not needed, moreover the conductive element can further include an extending portion; the present invention may be capable of affording a thinner electrical device thickness and enhanced reliability.

Abstract: Substrate for electrical devices is disclosed. An embodiment for the substrate comprised of an insulator and a conductive element(s), wherein the conductive element embedded in the insulator, said conductive element also enables to be comprised of an upper portion(s) and a lower portion(s) which are unitary and stack; wherein the surfaces of said conductive element contacted with said insulator enables to be increased, then said conductive layer can be held by said insulator more securely, in this manner, it enables to be prevented said conductive element from peeling off said insulator, and then the reliability of said substrate in accordance with the present invention enables to be enhanced; meanwhile, said substrate can further include a chip which is embedded therein, in order that said substrate being capable of affording a thinner electrical device thickness and enhanced reliability.

Abstract: Substrate for electrical devices is disclosed. An embodiment for the substrate comprised of an insulator, a conductive element(s) and a conductive material(s), wherein the conductive element embedded in the insulator, and two surfaces of the conductive element exposed to two surfaces of the insulator for electrical connection respectively, wherein the upper surface of conductive element is below the upper surface of insulator and is plated by the conductive material, meanwhile the conductive element include a protruding portion which is protruded the insulator, in this manner, solder balls are not needed, moreover the conductive element can further include an extending portion; the present invention may be capable of affording a thinner electrical device thickness and enhanced reliability.

Abstract: Substrate for electrical devices is disclosed. An embodiment for the substrate comprised of an insulator, a conductive element(s) and a conductive material(s), wherein the conductive element embedded in the insulator, and two surfaces of the conductive element exposed to two surfaces of the insulator for electrical connection respectively, wherein the upper surface of conductive element is below the upper surface of insulator and is plated by the conductive material, meanwhile the conductive element include a protruding portion which is protruded the insulator, in this manner, solder balls are not needed, moreover the conductive element can further include an extending portion; the present invention may be capable of affording a thinner electrical device thickness and enhanced reliability.

Abstract: Substrate for electrical devices and methods of manufacturing such substrate are disclosed. An embodiment for the substrate comprised of an insulator and a plurality of conductive elements, wherein the conductive elements embedded in the insulator, and two surfaces of the conductive element exposed to two surfaces of the insulator for electrical connection respectively, meanwhile a portion of conductive element may protrude the insulator, in this manner, solder balls are not needed, moreover the conductive element of substrate may further include either an extending portion or a protruding portion, and the present invention may be capable of affording a thinner electrical device thickness, enhanced reliability, and a decreased cost in production.

Abstract: A PLL is provided, comprising a first divider, a PFD, a loop filter, a VCO, a second divider and a controller. The first divider receives a reference signal and divides the reference signal by R to obtain a divided signal. The PFD compares the divided signal and a feedback signal to generate a compared The VCO selects one of a plurality of operating curves for oscillation based on a selection signal, and generates an oscillation signal based on an operating voltage generated by signal the loop filter. The second divider divides the oscillation signal by N to obtain the feedback signal. The controller operates in an initial mode to recursively determine the selection signal by calculating differences of the feedback signal and the divided signal. When the selection signal converges to stable, the PLL switches to a normal mode to operate on the corresponding operating curve.

Abstract: A heat spreader for electrical device is disclosed, a portion of said heat spreader is above and corresponding to a chip which is coupled with a base of electrical device. An embodiment for the heat spreader comprised of: a first portion, second portion, connecting portion, supporting portion and a side edge, said connecting portion is between said first portion and said second portion, said supporting portion coupled with the base of electrical device, said supporting portion is connected to the periphery of said first portion in order that said chip can be accommodated in said heat spreader; according to the heat spreader of the present invention, (i). Due to the side edge of said heat spreader can be protruded and exposed to the side wall of encapsulant, in this manner. Not only a larger chip can be placed in the heat spreader but the heat dissipation for said chip becomes more effective. (ii).

Abstract: Substrate for electrical devices and methods of manufacturing such substrate are disclosed. An embodiment for the substrate comprised of an insulator and a plurality of conductive elements, wherein the insulator having a recess. The conductive elements embedded in the insulator. The conductive elements extend from the insulator surface to the recess. There are two portions of the conductive elements for electrical connection respectively, wherein a portion of conductive element may protrude the insulator surface for electrical connection. In this manner, solder balls are not needed. Moreover, the substrate of the present invention may also comprise an adhesive mean, which is between the conductive elements and the insulator. In addition, the substrate may further comprise a submember such as a chip, heat spreader etc., and the present invention may be capable of affording a thinner electrical device thickness, enhanced reliability, and a decreased cost in production.

Abstract: A method for automatic frequency tuning in a phase lock loop suitable for use in multi-band VCO wireless systems having very limited initial frequency lock times is disclosed. A predetermined subset of VCOs out of a larger bank of VCOs is selected to serve as interpolation points. The interpolation point VCOs are pre-calibrated with a predetermined voltage and the resultingly generated frequency for each of the interpolation point VCOs is stored into memory as a (frequency, VCO) pair, one pair for each interpolation point VCO. When a desired frequency then is given to the system, an appropriate VCO is selected by interpolation using the (frequency, VCO) pairs of the two most adjacent interpolation points for tracking and locking.

Abstract: A method for automatic frequency tuning in a phase lock loop suitable for use in multi-band VCO wireless systems having very limited initial frequency lock times is disclosed. A predetermined subset of VCOs out of a larger bank of VCOs is selected to serve as interpolation points. The interpolation point VCOs are pre-calibrated with a predetermined voltage and the resultingly generated frequency for each of the interpolation point VCOs is stored into memory as a (frequency, VCO) pair, one pair for each interpolation point VCO. When a desired frequency then is given to the system, an appropriate VCO is selected by interpolation using the (frequency, VCO) pairs of the two most adjacent interpolation points for tracking and locking.

Abstract: Synthesizer and calibrating method utilizing same. The frequency synthesizer modulates input signals comprising a phase locked loop circuit. The phase locked loop circuit comprises a phase frequency detector for generating a first signal, a low pass filter for outputting a filtered control signal derived from the received first signal, a voltage control oscillator for generating an output signal with a first frequency based on the control signal, a frequency divider dividing the first frequency for output to the input terminal of the phase frequency detector, a modulator coupled to the frequency divider, a pre-emphasis filter receiving and filtering the input signal for output to the modulator, and an auto loop gain calibration circuit, receiving the control signal, and calculating a current gain of the control signal in accordance with the voltage of the control signal to compensate for the frequency response mismatch between the pre-emphasis filter and the frequency synthesizer.

Abstract: A PLL is provided, comprising a first divider, a PFD, a loop filter, a VCO, a second divider and a controller. The first divider receives a reference signal and divides the reference signal by R to obtain a divided signal. The PFD compares the divided signal and a feedback signal to generate a compared The VCO selects one of a plurality of operating curves for oscillation based on a selection signal, and generates an oscillation signal based on an operating voltage generated by signal the loop filter. The second divider divides the oscillation signal by N to obtain the feedback signal. The controller operates in an initial mode to recursively determine the selection signal by calculating differences of the feedback signal and the divided signal. When the selection signal converges to stable, the PLL switches to a normal mode to operate on the corresponding operating curve.

Abstract: A radio frequency (RF) receiver is provided, comprising an antenna, a low noise amplifier, a down converter, a first analog to digital converter (ADC), a second ADC, a digital up converter. The antenna receives an RF signal, and the LNA coupled to the antenna amplifies the RF signal. The down converter, coupled to the LNA, down converts the RF signal to generate an in-phase baseband signal and a quadrature baseband signal. The first ADC, coupled to the down converter, digitizes the in-phase baseband signal to an in-phase digital signal. The second ADC, coupled to the down converter, digitizes the quadrature baseband signal to a quadrature digital signal. The digital up converter, coupled to the first and second ADCs, up converts the in-phase digital signal and quadrature digital signal to generate an intermediate frequency (IF) signal.

Abstract: A demodulation method and apparatus are provided. An RF signal is down converted to generate a first in-phase signal and a first quadrature signal of a first frequency. Limiting amplification is performed on the first in-phase signal and the first quadrature signal to generate a second in-phase signal and a second quadrature signal. The frequency of the second in-phase and quadrature signals are up converted to a third in-phase signal and a quadrature signal of a second frequency. The third in-phase and quadrature signals are up converted to generate an intermediate frequency (IF) signal of a third frequency.

Abstract: A submember for electrical device is disclosed. Said submember is mounted on a chip of electrical device. An embodiment for the submember comprised of an insulator and a plurality of conductive elements, wherein the conductive elements embedded in the insulator and a portion of conductive element exposed to the insulator for electrical connection, then (i). the reliability of submember is enhanced; (ii). the material of insulator enables to be saved; and (iii). the thickness of submember is thinner and the heat dissipation of chip enhanced; moreover, a portion of the conductive element may be protruding the insulator for avoiding a short-circuited problem of conductive wire, moreover, the conductive element may be staircase-shaped, then, not only the reliability of submember is enhanced, but the short circuit problem of conductive wire is also avoided; the conductive element may further include an extending portion, furthermore, the conductive element may be placed in a cavity as required.