Abstract: A method for enhancing adhesion between adjacent dielectric layers, particularly in the formation of trenches and vias in the layers during the fabrication of semiconductor integrated circuits on wafer substrates. The method may include providing a via dielectric layer on a substrate above a metal conductive layer in the substrate, providing an adhesive layer on the via dielectric layer, providing a trench dielectric layer on the adhesive layer, etching a via in the via dielectric layer, etching a trench in the trench dielectric layer, filling the via and trench with a metal filling layer, and planarizing the filling layer. The adhesive layer between the via dielectric layer and the trench dielectric layer prevents CMP-induced peeling during the planarization step, and cracking of the layers during the package step.