Patents by Inventor Chung Chi

Chung Chi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11168198
    Abstract: A recycled polyester fiber is provided. The recycled polyester fiber is made of a raw material by melt spinning. The raw material includes 95.0 wt % to 99.99 wt % recycled polyester pellet formed from recycled bottle chip and 0.01 wt % to 5.0 wt % titanium dioxide slurry. Based on the total weight of the titanium dioxide slurry, the titanium dioxide slurry includes 20 wt % to 50 wt % bio-oil acting as carrier, 50 wt % to 80 wt % titanium dioxide powder, 0.1 wt % to 5 wt % dispersant, 0.01 wt % to 3 wt % antioxidant, and 0.001 wt % to 0.1 wt % dye.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: November 9, 2021
    Assignee: NAN YA PLASTICS CORPORATION
    Inventors: Te-Chao Liao, Chung-Chi Su, Chia-Sheng Lai
  • Publication number: 20210343867
    Abstract: A method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a liner over the fin; performing a surface treatment process to convert an upper layer of the liner distal to the fin into a conversion layer, the conversion layer comprising an oxide or a nitride of the liner; forming isolation regions on opposing sides of the fin after the surface treatment process; forming a gate dielectric over the conversion layer after forming the isolation regions; and forming a gate electrode over the fin and over the gate dielectric.
    Type: Application
    Filed: July 16, 2021
    Publication date: November 4, 2021
    Inventors: Wan-Yi Kao, Chung-Chi Ko
  • Patent number: 11143159
    Abstract: A Magnus rotor is provided. The Magnus rotor is located in a flowing fluid and driven to rotate by a power source. The Magnus rotor includes a Magnus rotor main body and a blade assembly. The Magnus rotor main body includes a cylinder side wall, a first end and a second end. The first end and the second end are disposed in one end and the other end of the cylinder side wall, respectively. The Magnus rotor is rotated around an axis connected between a first center point of the first end and a second center point of the second end. The blade assembly includes a plurality of blades which are disposed around the first end. Each blade is inclined toward a direction. A gap is formed between each two adjacent blades. Each gap is formed as a flowing channel for allowing the fluid to flow therethrough.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: October 12, 2021
    Inventor: Chung-Chi Chou
  • Publication number: 20210294772
    Abstract: In one embodiment, an apparatus includes: a plurality of cores to execute instructions; a firmware agent to execute a first firmware; a Peripheral Component Interconnect Express (PCIe) interface to communicate with a device via a PCIe link; and a boot agent coupled to the PCIe interface to download the PCIe firmware from a non-volatile memory and provide the PCIe firmware to the PCIe interface. The PCIe interface may receive a PCIe firmware for the PCIe interface before the firmware agent is to receive the first firmware. Other embodiments are described and claimed.
    Type: Application
    Filed: June 7, 2021
    Publication date: September 23, 2021
    Inventors: Amit Kumar Srivastava, Divya Gupta, Michael Karas, James Mitchell, Malay Trivedi, Chung-Chi Wang
  • Publication number: 20210287948
    Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, the first epitaxial source/drain region, and a protection layer between the first epitaxial source/drain region and the first gate spacer and between the first gate spacer and the first gate stack.
    Type: Application
    Filed: May 28, 2021
    Publication date: September 16, 2021
    Inventors: Shu Ling Liao, Chung-Chi Ko
  • Publication number: 20210265264
    Abstract: An interconnect structure includes an interconnect structure includes an etching stop layer; a dielectric layer and an insert layer on the etching stop layer, and a conductive feature in the dielectric layer, the insert layer and the etching stop layer. A material of the insert layer is different from the dielectric layer and the etching stop layer.
    Type: Application
    Filed: February 26, 2020
    Publication date: August 26, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Cheng Chou, Chung-Chi Ko, Tze-Liang Lee
  • Publication number: 20210257482
    Abstract: A method for fabricating a semiconductor device that includes a merged source/drain feature extending between two adjacent fin structures. An air gap is formed under the merged source/drain feature. Forming the epitaxial feature includes growing a first epitaxial feature having a first portion over the first fin structure and a second portion over the second fin structure, growing a second epitaxial feature over the first and second portions of the first epitaxial feature, and growing a third epitaxial feature over the second epitaxial feature. The second epitaxial feature includes a merged portion between the first fin structure and the second fin structure.
    Type: Application
    Filed: November 12, 2020
    Publication date: August 19, 2021
    Inventors: Feng-Ching CHU, Chung-Chi WEN, Wei-Yuan LU, Feng-Cheng YANG, Yen-Ming CHEN
  • Patent number: 11075123
    Abstract: A method for forming a semiconductor structure is provided. The method includes patterning a semiconductor substrate to form a first semiconductor fin and a second semiconductor fin, and depositing a first dielectric material on the first and second semiconductor fins. There is a trench between the first and second semiconductor fins. The method also includes depositing a semiconductor material on the first dielectric material, heating the semiconductor material to cause the semiconductor material to flow to a bottom region of the trench, filling a top region of the trench with a second dielectric material, and heating the first dielectric material, the second dielectric material, and the semiconductor material to form an isolation structure between the first and second semiconductor fins.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Yi Kao, Chung-Chi Ko, Wei-Jin Li
  • Publication number: 20210226024
    Abstract: Embodiments of the present disclosure relate to a method of forming a low-k dielectric material, for example, a low-k gate spacer layer in a FinFET device. The low-k dielectric material may be formed using a precursor having a general chemical structure comprising at least one carbon atom bonded between two silicon atoms. A target k-value of the dielectric material may be achieved by controlling carbon concentration in the dielectric material.
    Type: Application
    Filed: April 5, 2021
    Publication date: July 22, 2021
    Inventors: Wan-Yi Kao, Chung-Chi Ko
  • Patent number: 11069812
    Abstract: A method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a liner over the fin; performing a surface treatment process to convert an upper layer of the liner distal to the fin into a conversion layer, the conversion layer comprising an oxide or a nitride of the liner; forming isolation regions on opposing sides of the fin after the surface treatment process; forming a gate dielectric over the conversion layer after forming the isolation regions; and forming a gate electrode over the fin and over the gate dielectric.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yi Kao, Chung-Chi Ko
  • Publication number: 20210202254
    Abstract: A device includes a first dielectric layer, a first conductor, an etch stop layer, a second dielectric layer, and a second conductor. The first conductor is in the first dielectric layer. The etch stop layer is over the first dielectric layer. The etch stop layer has a first surface facing the first dielectric layer and a second surface facing away from the first dielectric layer, and a concentration of carbon in the etch stop layer periodically varies from the first surface to the second surface. The second dielectric layer is over the etch stop layer. The second conductor is in the second dielectric layer and the etch stop layer and electrically connected to the first conductor.
    Type: Application
    Filed: March 12, 2021
    Publication date: July 1, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Yun PENG, Chung-Chi KO, Keng-Chu LIN
  • Publication number: 20210202235
    Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.
    Type: Application
    Filed: March 15, 2021
    Publication date: July 1, 2021
    Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
  • Patent number: 11049763
    Abstract: A method includes forming a carbon-containing layer with a carbon atomic percentage greater than about 25 percent over a first hard mask layer, forming a capping layer over the carbon-containing layer, forming a first photo resist over the capping layer, and etching the capping layer and the carbon-containing layer using the first photo resist as a first etching mask. The first photo resist is then removed. A second photo resist is formed over the capping layer. The capping layer and the carbon-containing layer are etched using the second photo resist as a second etching mask. The second photo resist is removed. A third photo resist under the carbon-containing layer is etched using the carbon-containing layer as etching mask. A dielectric layer underlying the third photo resist is etched to form via openings using the third photo resist as etching mask. The via openings are filled with a conductive material.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: June 29, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Kai Chen, Jung-Hau Shiu, Chia Cheng Chou, Chung-Chi Ko, Tze-Liang Lee, Chih-Hao Chen, Shing-Chyang Pan
  • Publication number: 20210163109
    Abstract: A vertical axis fluid energy conversion device is provided. The vertical axis fluid energy conversion device includes at least one lift blade and at least one Magnus rotor. A power source drives the Magnus rotor to rotate and the Magnus lift force is produced. The Magnus rotor is connected with a main shaft through a connection component. Consequently, the main shaft is rotated and the lift blade is also revolved. The flow field of the vertical axis fluid energy conversion device is less influenced by the Magnus rotor. The performance of the lift blade is better. The whole efficiency is enhanced. The vertical axis fluid energy conversion device is self-starting through the Magnus rotor. The power source only drives the Magnus rotor to rotate, but not drive the whole device. Therefore, the vertical axis fluid energy conversion device has advantages of low cost and low energy consumption.
    Type: Application
    Filed: November 19, 2020
    Publication date: June 3, 2021
    Inventor: Chung-Chi Chou
  • Patent number: 11024550
    Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, the first epitaxial source/drain region, and a protection layer between the first epitaxial source/drain region and the first gate spacer and between the first gate spacer and the first gate stack.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu Ling Liao, Chung-Chi Ko
  • Publication number: 20210139628
    Abstract: A curing agent composition and a curing agent coating formula thereof are provided. The curing agent composition includes 5 to 25 wt % of an ester group-containing amine end group adduct, 2 to 25 wt % of a C8-C22 hydrophobic saturated or unsaturated fatty amine, 2 to 25 wt % of a polyamine compound, 2 to 20 wt % of a silane compound, and 10 to 60 wt % of an ether solvent.
    Type: Application
    Filed: May 29, 2020
    Publication date: May 13, 2021
    Inventors: TE-CHAO LIAO, SEN-HUANG HSU, CHUNG-CHI SU, CHUAN CHOU, Jui-Jung Lin
  • Publication number: 20210125874
    Abstract: A method includes forming a dummy gate stack over a semiconductor region of a wafer, and depositing a gate spacer layer using Atomic Layer Deposition (ALD) on a sidewall of the dummy gate stack. The depositing the gate spacer layer includes performing an ALD cycle to form a dielectric atomic layer. The ALD cycle includes introducing silylated methyl to the wafer, purging the silylated methyl, introducing ammonia to the wafer, and purging the ammonia.
    Type: Application
    Filed: January 4, 2021
    Publication date: April 29, 2021
    Inventors: Wan-Yi Kao, Chung-Chi Ko
  • Publication number: 20210122876
    Abstract: A curing agent and method for producing the same are provided, the method includes: esterification reaction: reacting a polyhydric alcohol with a polybasic acid anhydride to obtain an ester-based emulsifier (A); chain extension reaction: reacting an ester-based emulsifier (A) with a bifunctional epoxy resin to obtain a polymer intermediate (B); and reacting the polymer intermediate (B) with a polyamine compound to obtain a curing agent (C).
    Type: Application
    Filed: August 31, 2020
    Publication date: April 29, 2021
    Inventors: TE-CHAO LIAO, SEN-HUANG HSU, CHUNG-CHI SU, CHUAN CHOU, Jui-Jung Lin
  • Patent number: 10971589
    Abstract: Embodiments of the present disclosure relate to a method of forming a low-k dielectric material, for example, a low-k gate spacer layer in a FinFET device. The low-k dielectric material may be formed using a precursor having a general chemical structure comprising at least one carbon atom bonded between two silicon atoms. A target k-value of the dielectric material may be achieved by controlling carbon concentration in the dielectric material.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yi Kao, Chung-Chi Ko
  • Patent number: 10957543
    Abstract: A method includes forming an interlayer dielectric (ILD) and a gate structure over a substrate. The gate structure is surrounded by the ILD. The gate structure is etched to form a recess. A first dielectric layer is deposited over sidewalls and a bottom of the recess and over a top surface of the ILD using a first Si-containing precursor. A second dielectric layer is deposited over and in contact with the first dielectric layer using a second Si-containing precursor different from the first Si-containing precursor. A third dielectric layer is deposited over and in contact with the second dielectric layer using the first Si-containing precursor. Portions of the first, second, and third dielectric layer over the top surface of the ILD are removed.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Yun Peng, Chung-Chi Ko, Keng-Chu Lin