Abstract: A device includes an electrical circuit having a first set of circuit elements. The device further includes a first set of conductive pillars over a first side of a substrate. The device further includes a first conductive rail electrically connected to each of the first set of conductive pillars, wherein each of the first set of conductive pillars is electrically connected to each of the first set of circuit elements by the first conductive rail. The device further includes a first plurality of power pillars extending through the substrate, wherein each of the first plurality of power pillars is electrically connected to the first conductive rail.

Abstract: A ferroelectric memory device and a semiconductor die are provided. The ferroelectric memory device includes a gate electrode; a channel layer, overlapped with the gate electrode; source/drain contacts, in contact with separate ends of the channel layer; a ferroelectric layer, lying between the gate electrode and the channel layer; and a first insertion layer, extending in between the ferroelectric layer and the channel layer, and comprising a metal carbonitride or a metal nitride.

Abstract: A semiconductor device includes an active region over a substrate extending along a first lateral direction. The semiconductor device includes a number of first conductive structures operatively coupled to the active region. The first conductive structures extend along a second lateral direction. The semiconductor device includes a number of second conductive structures disposed above the plurality of first conductive structures. The second conductive structures extend along the first lateral direction. The semiconductor device includes a first capacitor having a first electrode and a second electrode. The first electrode includes one of the first conductive structures and the active region, and the second electrode includes a first one of the second conductive structures. Each of the active region and the first conductive structures is electrically coupled to a power rail structure configured to carry a supply voltage.

Abstract: A device includes a control circuit, a scope circuit, a first logic gate and a second logic gate. The control circuit is configured to generate a first control signal according to a voltage signal and a delayed signal. The scope circuit is configured to generate a first current signal in response to the first control signal and the voltage signal. The first logic gate is configured to perform a first logical operation on the voltage signal and one of the voltage signal and the delayed signal to generate a second control signal. The second logical gate configured to perform a second logical operation on the second control signal and a test control signal to generate a second current signal.

Abstract: A semiconductor device includes an active region over a substrate extending along a first lateral direction. The semiconductor device includes a number of first conductive structures operatively coupled to the active region. The first conductive structures extend along a second lateral direction. The semiconductor device includes a number of second conductive structures disposed above the plurality of first conductive structures. The second conductive structures extend along the first lateral direction. The semiconductor device includes a first capacitor having a first electrode and a second electrode. The first electrode includes one of the first conductive structures and the active region, and the second electrode includes a first one of the second conductive structures. Each of the active region and the first conductive structures is electrically coupled to a power rail structure configured to carry a supply voltage.

Abstract: An integrated circuit includes an array of metal conducting lines in a metal layer overlying an insulation layer supported by a substrate, a first metal segment lineup having multiple metal segments in the metal layer between a first metal conducting line and a second metal conducting line in the array of metal conducting lines, and an electric circuit having a first input and a second input. The first input is connected to the first metal conducting line and the second input is connected to the second metal conducting line, and a first length of the first metal conducting line is equal to a second length of the second metal conducting line.

Abstract: A semiconductor device includes a metal-oxide-metal (MOM) cell including a first bus at a first elevation and extending along a first direction, and a second bus at a second elevation, extending along a second direction different from the first direction, and electrically connected to the first bus through a via. The MOM cell also includes a first group of fingers at the first elevation and extending along the first direction; and a second group of fingers at the second elevation and extending along the second direction. Each finger of the first group of fingers is electrically connected to the second bus through a corresponding via, each finger of the second group of fingers is electrically connected to the first bus through a corresponding via, and each finger of the first group of fingers overlaps each finger of the second group of fingers.

Abstract: A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; generating a circuit layout of the integrated circuit when the circuit design meets the predetermined specification; modifying a pillar density of the initial power delivery network repeatedly when the circuit design does not meet the predetermined specification until the circuit design meets the predetermined specification to generate a circuit layout of the integrated circuit; and performing a post-layout simulation to the circuit layout.

Abstract: A semiconductor device includes a capacitor having a first conductor plate, a second conductor plate, and a portion of a dielectric layer interposed therebetween. The semiconductor device includes a plurality of first contact structures in electrical contact with the first conductor plate. The semiconductor device includes a plurality of second contact structures in electrical contact with the second conductor plate. The plurality of first contact structures and the plurality of second contact structures are laterally arranged in a checkboard pattern, thereby causing each of the plurality of first contact structures to be surrounded by respective four of the plurality of second contact structures.

Abstract: A delay measurement system and a measurement method are provided. The delay measurement system includes a delay control device and a comparator. The delay control device is configured to generate a second signal in response to a first signal, wherein a rising edge of the second signal delays a first delay time with respect to a rising edge of the first signal, and the first delay time is controlled in response to an output signal of a comparator. The comparator is configured to compare the first delay time with a second delay time and output the output signal, wherein a rising edge of a third signal delays the second delay time with respect to the rising edge of the first signal, and the third signal is generated by a device under test (DUT) in response to the first signal.

Abstract: A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; generating a circuit layout of the integrated circuit when the circuit design meets the predetermined specification; and adding at least one additional conductive pillar or at least one additional power rail in the initial power delivery network according to a relationship of a pillar density of the initial power delivery network and a maximum pillar density when the circuit design does not meet the predetermined specification.

Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.

Abstract: Capacitor structures with low capacitances are disclosed. In one example, a capacitor structure is disclosed. The capacitor structure includes a first electrode and a second electrode. The first electrode comprises a first metal finger. The second electrode comprises a second metal finger and a third metal finger that are parallel to each other and to the first metal finger. The first metal finger is formed between the second metal finger and the third metal finger. The capacitor structure further includes: a fourth metal finger formed as a dummy metal finger between the first metal finger and the second metal finger, and a fifth metal finger formed as a dummy metal finger between the first metal finger and the third metal finger. The fourth metal finger and the fifth metal finger are parallel to the first metal finger.

Abstract: The present disclosure provides a circuitry. The circuitry includes a comparator and a signal correlated circuit. The comparator includes a first input terminal, a second input terminal, and an output terminal. The signal correlated circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is coupled to receive a first input signal. The second input terminal is coupled to receive a second input signal independent from the first input signal. The first output terminal is configured to generate a first output signal and to send the first output signal to the first input terminal of the comparator. The second output terminal is configured to generate a second output signal and to send the second output signal to the second input terminal of the comparator. The first output signal and the second output signal are correlated.

Abstract: A device includes a control circuit, a scope circuit, a first logic gate and a second logic gate. The control circuit is configured to generate a first control signal according to a voltage signal and a delayed signal. The scope circuit is configured to generate a first current signal in response to the first control signal and the voltage signal. The first logic gate is configured to perform a first logical operation on the voltage signal and one of the voltage signal and the delayed signal to generate a second control signal. The second logical gate configured to perform a second logical operation on the second control signal and a test control signal to generate a second current signal.

Abstract: The present disclosure provides a circuitry. The circuitry includes a comparator and a signal correlated circuit. The comparator includes a first input terminal, a second input terminal, and an output terminal. The signal correlated circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is coupled to receive a first input signal. The second input terminal is coupled to receive a second input signal independent from the first input signal. The first output terminal is configured to generate a first output signal and to send the first output signal to the first input terminal of the comparator. The second output terminal is configured to generate a second output signal and to send the second output signal to the second input terminal of the comparator. The first output signal and the second output signal are correlated.

Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.

Abstract: A device includes a control circuit, a scope circuit, and a time-to-current converter. The control circuit is configured to receive a voltage signal from a voltage-controlled oscillator, delay the voltage signal for a delay time to generate a first control signal, and to generate a second control signal according to the first control signal and the voltage signal. The scope circuit is configured to generate a first current signal in response to the second control signal and the voltage signal. The time-to-current converter is configured generate a second current signal according to the first control signal, the voltage signal, a first switch signal, and a test control signal.

Abstract: The present disclosure provides a circuitry. The circuitry includes a comparator and a signal correlated circuit. The comparator includes a first input terminal, a second input terminal, and an output terminal, The signal correlated circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is coupled to receive a first input signal. The second input terminal is coupled to receive a second input signal independent from the first input signal. The first output terminal is configured to generate a first output signal and to send the first output signal to the first input terminal of the comparator. The second output terminal is configured to generate a second output signal and to send the second output signal to the second input terminal of the comparator. The first output signal and the second output signal are correlated.

Abstract: A device includes an electrical circuit having a first set of circuit elements. The device further includes a first set of conductive pillars over a first side of a substrate. The device further includes a first conductive rail electrically connected to each of the first set of conductive pillars, wherein each of the first set of conductive pillars is electrically connected to each of the first set of circuit elements by the first conductive rail. The device further includes a first plurality of power pillars extending through the substrate, wherein each of the first plurality of power pillars is electrically connected to the first conductive rail.