Patents by Inventor Chung-Chieh Yang
Chung-Chieh Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20180374811Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a carrier having a first surface and including a power layer adjacent to the first surface of the carrier, an electrical component disposed on the first surface of the carrier, and a conductive element disposed on the first surface of the carrier. The electrical component is electrically connected to the power layer. The conductive element is electrically connected to the power layer. The conductive element, the power layer, and the electrical component form a power-transmission path.Type: ApplicationFiled: June 22, 2017Publication date: December 27, 2018Inventors: Chung-Chieh YANG, Sheng-Ming WANG, Tien-Szu CHEN
-
Patent number: 10161967Abstract: A device is disclosed that includes a control circuit, a scope circuit and a time-to-current converter. The control circuit configured to delay a voltage signal for a delay time to generate a first control signal, and to generate a second control signal according to the first control signal and the voltage signal. The scope circuit configured to generate a first current signal in response to the second control signal and the voltage signal. The time-to-current converter configured to generate a second current signal according to the first control signal and the voltage signal.Type: GrantFiled: January 9, 2016Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Peng Hsieh, Chih-Chiang Chang, Chung-Chieh Yang
-
Patent number: 9966963Abstract: A frequency synthesizer comprising a reference oscillator configured to generate a first clock signal with a reference frequency and a divider controller configured to receive the first clock signal, a second clock signal, and a multiplier value. The divider controller is configured to obtain a ratio of a frequency of the first clock signal to a frequency of the second clock signal and divide the resulting ratio by the multiplier value to obtain controller output value. A divider is configured to receive the first clock signal and controller output value and output an output clock signal with a frequency equal to the frequency of the first clock signal divided by the controller output value.Type: GrantFiled: September 23, 2016Date of Patent: May 8, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Mao-Hsuan Chou, Chih-Chiang Chang, Chung-Chieh Yang
-
Publication number: 20180091161Abstract: A frequency synthesizer comprising a reference oscillator configured to generate a first clock signal with a reference frequency and a divider controller configured to receive the first clock signal, a second clock signal, and a multiplier value. The divider controller is configured to obtain a ratio of a frequency of the first clock signal to a frequency of the second clock signal and divide the resulting ratio by the multiplier value to obtain controller output value. A divider is configured to receive the first clock signal and controller output value and output an output clock signal with a frequency equal to the frequency of the first clock signal divided by the controller output value.Type: ApplicationFiled: September 23, 2016Publication date: March 29, 2018Inventors: Mao-Hsuan Chou, Chih-Chiang Chang, Chung-Chieh Yang
-
Publication number: 20170365552Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.Type: ApplicationFiled: August 31, 2017Publication date: December 21, 2017Inventors: Chia-Hsin HU, Yu-Chiun LIN, Yi-Hsuan CHUNG, Chung-Peng HSIEH, Chung-Chieh YANG, Po-Nien CHEN
-
Publication number: 20170338377Abstract: The present invention is a light emitting diode (LED) device including a substrate, a buffer layer, a first conductivity type semiconductor layer, a light emitting layer, an interlayer, an electron blocking layer, and a second conductivity type semiconductor layer. The thickness of the interlayer is substantially thinner than the thickness of the electron blocking layer. In an embodiment of the present invention, the interlayer is doped with a p-type dopant, and the electron blocking layer is doped with a p-type dopant, and the concentration of the p-type dopant of the interlayer is lower than the concentration of the p-type dopant of the electron blocking layer.Type: ApplicationFiled: December 2, 2016Publication date: November 23, 2017Inventors: Chung-Chieh YANG, Te-Chung WANG
-
Patent number: 9773731Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.Type: GrantFiled: January 28, 2016Date of Patent: September 26, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Hsin Hu, Yu-Chiun Lin, Yi-Hsuan Chung, Chung-Peng Hsieh, Chung-Chieh Yang, Po-Nien Chen
-
Publication number: 20170221821Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.Type: ApplicationFiled: January 28, 2016Publication date: August 3, 2017Inventors: Chia-Hsin HU, Yu-Chiun LIN, Yi-Hsuan CHUNG, Chung-Peng HSIEH, Chung-Chieh YANG, Po-Nien CHEN
-
Publication number: 20170199228Abstract: A device is disclosed that includes a control circuit, a scope circuit and a time-to-current converter. The control circuit configured to delay a voltage signal for a delay time to generate a first control signal, and to generate a second control signal according to the first control signal and the voltage signal. The scope circuit configured to generate a first current signal in response to the second control signal and the voltage signal. The time-to-current converter configured to generate a second current signal according to the first control signal and the voltage signal.Type: ApplicationFiled: January 9, 2016Publication date: July 13, 2017Inventors: Chung-Peng HSIEH, Chih-Chiang CHANG, Chung-Chieh YANG
-
Publication number: 20170141263Abstract: The present invention relates to an ultraviolet light-emitting diode (LED), which includes a gradual superlattice layer. The gradual superlattice layer comprises a first superlattice layer and a second superlattice layer. The first superlattice layer includes a multi-layer structure having repetitive stacks of a unit formed by a first layer and a second layer. The second superlattice layer includes a multi-layer structure having repetitive stacks of a unit formed by a third layer and a fourth layer. The concentrations of aluminum in the first, second, third, and fourth layers decrease sequentially. By disposing the gradual superlattice layer, the quality of the epitaxial structure may be improved apparently.Type: ApplicationFiled: November 9, 2016Publication date: May 18, 2017Inventors: CHUNG-CHIEH YANG, TE-CHUNG WANG
-
Publication number: 20170117368Abstract: A compound semiconductor film structure includes a substrate, a first compound semiconductor epitaxial layer and a second compound semiconductor epitaxial layer. The substrate has a top surface. The first compound semiconductor epitaxial layer is formed on the top surface and has an epitaxial interface and at least one recess, wherein the epitaxial interface is disposed on one side of the first compound semiconductor epitaxial layer opposite to the side of the first compound semiconductor epitaxial layer facing the top surface, and the at least one recess is formed in the first compound semiconductor epitaxial layer. The second compound semiconductor epitaxial layer formed on the epitaxial interface. The top surface and the bottom of recess are separated by a distance substantially ranging between 0.8 ?m and 1.3 ?m.Type: ApplicationFiled: September 12, 2016Publication date: April 27, 2017Inventor: Chung-Chieh Yang
-
Patent number: 9500687Abstract: A circuit for measuring the gain of an operational amplifier is provided. The circuit comprises a first operational amplifier, a first resistive device and a second resistive device. The first operational amplifier has an original gain and includes a first input terminal and a second input terminal. The first resistive device is coupled between the first input terminal and the second input terminal of the first operational amplifier. The second resistive device is coupled to the second input terminal of the first operational amplifier. The first resistive device and the second resistive device are configured to reduce a predetermined amount of gain from the original gain of the first operational amplifier.Type: GrantFiled: March 21, 2014Date of Patent: November 22, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chung-Peng Hsieh, Yung-Chow Peng, Chung-Chieh Yang, Chung-Ting Lu, Chih-Chiang Chang
-
Patent number: 9448281Abstract: A methodology and circuits for integrated circuit design are provided. A first electronic design file for an integrated circuit is provided. The first electronic design file for the integrated circuit has a timing measurement circuit thereon. Based on the first electronic design file, a number of integrated circuits are manufactured. These manufactured integrated circuits have respective timing measurement circuits arranged at predetermined locations thereon. The timing measurement circuits are used to measure a number of respective timing delay values, which are subject to manufacturing variation, on the integrated circuits. The measured timing delay values are used to set how an auto-place and route tool arranges blocks in a second electronic design file, which is routed after the timing delay values are measured, to account for any measured manufacturing variation.Type: GrantFiled: December 19, 2013Date of Patent: September 20, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jinn-Yeh Chien, Yung-Chow Peng, Chung-Chieh Yang, Kuan-Yu Lin
-
Patent number: 9424384Abstract: A method of density-controlled floorplan design for integrated circuits having a plurality of blocks includes positioning decoupling capacitor (DCAP) cells at least partially around a pattern density sensitive block. The method also includes changing at least a portion of a pattern density insensitive block adjacent to the pattern density sensitive block according to at least one pattern density rule.Type: GrantFiled: June 20, 2014Date of Patent: August 23, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Chieh Yang, Yung-Chow Peng, Chung-Peng Hsieh, Wen-Shen Chou, Chih-Chiang Chang
-
Publication number: 20150370946Abstract: A method of density-controlled floorplan design for integrated circuits having a plurality of blocks includes positioning decoupling capacitor (DCAP) cells at least partially around a pattern density sensitive block. The method also includes changing at least a portion of a pattern density insensitive block adjacent to the pattern density sensitive block according to at least one pattern density rule.Type: ApplicationFiled: June 20, 2014Publication date: December 24, 2015Inventors: Chung-Chieh YANG, Yung-Chow PENG, Chung-Peng HSIEH, Wen-Shen CHOU, Chih-Chiang CHANG
-
Publication number: 20150268297Abstract: A circuit for measuring the gain of an operational amplifier is provided. The circuit comprises a first operational amplifier, a first resistive device and a second resistive device. The first operational amplifier has an original gain and includes a first input terminal and a second input terminal. The first resistive device is coupled between the first input terminal and the second input terminal of the first operational amplifier. The second resistive device is coupled to the second input terminal of the first operational amplifier. The first resistive device and the second resistive device are configured to reduce a predetermined amount of gain from the original gain of the first operational amplifier.Type: ApplicationFiled: March 21, 2014Publication date: September 24, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: CHUNG-PENG HSIEH, YUNG-CHOW PENG, CHUNG-CHIEH YANG, CHUNG-TING LU, CHIH-CHIANG CHANG
-
Patent number: 9143116Abstract: A method of determining an effective capacitance of a ring oscillator free of short current. The method comprises determining a frequency of an oscillator signal communicated from a ring oscillator to an inverter via a first communication path. The first communication path has connectivity to a first voltage source, a ground path and the inverter. The first communication path is divided into a second communication path and a third communication path. The method further comprises determining a voltage line current. The method additionally comprises determining an effective capacitance of the ring oscillator based on a first voltage of the first voltage source, the voltage line current and the frequency of the oscillator signal communicated to the inverter along the third communication path.Type: GrantFiled: October 11, 2013Date of Patent: September 22, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Peng Hsieh, Chung-Ting Lu, Chung-Chieh Yang, Chih-Chiang Chang
-
Publication number: 20150177327Abstract: A methodology and circuits for integrated circuit design are provided. A first electronic design file for an integrated circuit is provided. The first electronic design file for the integrated circuit has a timing measurement circuit thereon. Based on the first electronic design file, a number of integrated circuits are manufactured. These manufactured integrated circuits have respective timing measurement circuits arranged at predetermined locations thereon. The timing measurement circuits are used to measure a number of respective timing delay values, which are subject to manufacturing variation, on the integrated circuits. The measured timing delay values are used to set how an auto-place and route tool arranges blocks in a second electronic design file, which is routed after the timing delay values are measured, to account for any measured manufacturing variation.Type: ApplicationFiled: December 19, 2013Publication date: June 25, 2015Inventors: Jinn-Yeh Chien, Yung-Chow Peng, Chung-Chieh Yang, Kuan-Yu Lin
-
Patent number: 9064079Abstract: An integrated circuit with a power layout includes at least one power grid cell. Each power grid cell includes a first power layer configured to be electrically coupled to a first power supply voltage, and a second power layer separate from the first power layer and configured to be electrically coupled to a second power supply voltage different from the first power supply voltage. The first power layer has conductive lines configured to surround a conductive element electrically connected to the second power layer.Type: GrantFiled: February 25, 2014Date of Patent: June 23, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Chung-Chieh Yang
-
Publication number: 20150102861Abstract: A method of determining an effective capacitance of a ring oscillator free of short current. The method comprises determining a frequency of an oscillator signal communicated from a ring oscillator to an inverter via a first communication path. The first communication path has connectivity to a first voltage source, a ground path and the inverter. The first communication path is divided into a second communication path and a third communication path. The method further comprises determining a voltage line current. The method additionally comprises determining an effective capacitance of the ring oscillator based on a first voltage of the first voltage source, the voltage line current and the frequency of the oscillator signal communicated to the inverter along the third communication path.Type: ApplicationFiled: October 11, 2013Publication date: April 16, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, INC.Inventors: Chung-Peng HSIEH, Chung-Ting LU, Chung-Chieh YANG, Chih-Chiang CHANG