Abstract: An integrated circuit structure includes: a first conductive plate disposed in a first layer on a semiconductor substrate; a second conductive plate disposed in a second layer on the semiconductor substrate; a plurality of conductive lines disposed in the first layer, for surrounding the first conductive plate; and a plurality of conductive vias arranged to couple the plurality of conductive lines to the second conductive plate; wherein the second layer is different from the first layer, and the first conductive plate is physically separated from the second conductive plate, the plurality of conductive lines, and the plurality of conductive vias.

Abstract: An integrated circuit structure includes: a first conductive plate disposed in a first layer on a semiconductor substrate; a second conductive plate disposed in a second layer on the semiconductor substrate; a plurality of conductive lines disposed in the first layer, for surrounding the first conductive plate; and a plurality of conductive vias arranged to couple the plurality of conductive lines to the second conductive plate; wherein the second layer is different from the first layer, and the first conductive plate is physically separated from the second conductive plate, the plurality of conductive lines, and the plurality of conductive vias.

Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.

Abstract: A bandgap reference circuit includes a current generating circuit, a switch circuit and a control circuit. The current generating circuit is triggered by a trigger signal, generated when the bandgap reference circuit starts up, to mirror a base current to generate a first current and a second current. The current generating circuit is arranged to output the first current when triggered by the triggered signal. The switch circuit is controlled by a switch control signal to be selectively coupled between the current generating circuit and a terminal coupled to a regulator. The switch circuit is arranged to, when coupled between the current generating circuit and the terminal, allow the current generating circuit to output the second current to the terminal and accordingly provide a bandgap voltage. When the first current reduces to a predetermined level, the control circuit activates generation of the switch control signal to control the switch circuit.

Abstract: Capacitor structures with low capacitances are disclosed. In one example, a capacitor structure is disclosed. The capacitor structure includes a first electrode and a second electrode. The first electrode comprises a first metal finger. The second electrode comprises a second metal finger and a third metal finger that are parallel to each other and to the first metal finger. The first metal finger is formed between the second metal finger and the third metal finger. The capacitor structure further includes: a fourth metal finger formed as a dummy metal finger between the first metal finger and the second metal finger, and a fifth metal finger formed as a dummy metal finger between the first metal finger and the third metal finger. The fourth metal finger and the fifth metal finger are parallel to the first metal finger.

Abstract: A noise detection circuit includes an analog-to-digital conversion (ADC) circuit and a noise event recognition circuit. The ADC circuit is configured to convert an analog signal outputted from a device under test (DUT) into a sequence of digital codes. The noise event recognition circuit, coupled to the ADC circuit, is configured to determine a noise count of the sequence of digital codes, and refer to the noise count to determine if a noise event occurs in the DUT. The noise count indicates a number of times a change in code values between two successive digital codes exceeds a predetermined value.

Abstract: A bandgap reference circuit includes a current generating circuit, a switch circuit and a control circuit. The current generating circuit is triggered by a trigger signal generated when the bandgap reference circuit starts up. The current generating circuit is arranged to generate a reference current according to the trigger signal. The switch circuit is controlled by a switch control signal to be selectively coupled between the current generating circuit and a regulator. The switch circuit is arranged to, when coupled between the current generating circuit and the regulator according to the switch control signal, provide a bandgap voltage to the regulator according to the reference current. The control circuit is coupled to the current generating circuit and the switch circuit, and is arranged to generate the switch control signal according to the trigger signal.

Abstract: A bandgap reference circuit includes a current generating circuit, a switch circuit and a control circuit. The current generating circuit is triggered by a trigger signal generated when the bandgap reference circuit starts up. The current generating circuit is arranged to generate a reference current according to the trigger signal. The switch circuit is controlled by a switch control signal to be selectively coupled between the current generating circuit and a regulator. The switch circuit is arranged to, when coupled between the current generating circuit and the regulator according to the switch control signal, provide a bandgap voltage to the regulator according to the reference current. The control circuit is coupled to the current generating circuit and the switch circuit, and is arranged to generate the switch control signal according to the trigger signal.

Abstract: Capacitor structures with low capacitances are disclosed. In one example, a capacitor structure is disclosed. The capacitor structure includes a first electrode and a second electrode. The first electrode comprises a first metal finger. The second electrode comprises a second metal finger and a third metal finger that are parallel to each other and to the first metal finger. The first metal finger is formed between the second metal finger and the third metal finger. The capacitor structure further includes: a fourth metal finger formed as a dummy metal finger between the first metal finger and the second metal finger, and a fifth metal finger formed as a dummy metal finger between the first metal finger and the third metal finger. The fourth metal finger and the fifth metal finger are parallel to the first metal finger.

Abstract: A semiconductor device is disclosed. In one example, the semiconductor device includes: an electronic component having a top surface, a bottom surface, and two end portions; a plurality of contacts disposed on the top surface; and a plurality of metal nodes disposed on the plurality of contacts. The plurality of contacts includes two end contacts disposed at the two end portions respectively and at least one intermediate contact disposed between the two end contacts. The plurality of metal nodes includes two end metal nodes disposed on the two end contacts respectively and at least one intermediate metal node disposed on the at least one intermediate contact.

Abstract: Capacitor structures with low capacitances are disclosed. In one example, a capacitor structure is disclosed. The capacitor structure includes a first electrode and a second electrode. The first electrode comprises a first metal finger. The second electrode comprises a second metal finger and a third metal finger that are parallel to each other and to the first metal finger. The first metal finger is formed between the second metal finger and the third metal finger. The capacitor structure further includes: a fourth metal finger formed as a dummy metal finger between the first metal finger and the second metal finger, and a fifth metal finger formed as a dummy metal finger between the first metal finger and the third metal finger. The fourth metal finger and the fifth metal finger are parallel to the first metal finger.

Abstract: A noise detection circuit includes an analog-to-digital conversion (ADC) circuit and a noise event recognition circuit. The ADC circuit is configured to convert an analog signal outputted from a device under test (DUT) into a sequence of digital codes. The noise event recognition circuit, coupled to the ADC circuit, is configured to determine a noise count of the sequence of digital codes, and refer to the noise count to determine if a noise event occurs in the DUT. The noise count indicates a number of times a change in code values between two successive digital codes exceeds a predetermined value.

Abstract: A semiconductor device is disclosed. In one example, the semiconductor device includes: an electronic component having a top surface, a bottom surface, and two end portions; a plurality of contacts disposed on the top surface; and a plurality of metal nodes disposed on the plurality of contacts. The plurality of contacts includes two end contacts disposed at the two end portions respectively and at least one intermediate contact disposed between the two end contacts. The plurality of metal nodes includes two end metal nodes disposed on the two end contacts respectively and at least one intermediate metal node disposed on the at least one intermediate contact.

Abstract: A bandgap reference circuit includes: a current generating circuit, a start-up circuit, a switch circuit, and a control circuit. The current generating circuit is arranged to generate a reference current according to a control signal on a control node. The start-up circuit is coupled to the current generating circuit and arranged to generate a trigger signal and output the trigger signal as the control signal when the bandgap reference circuit starts up. The switch circuit is coupled to the current generating circuit and arranged to generate a bandgap voltage according to the reference current, and the bandgap voltage is outputted to a regulator coupled to the bandgap reference circuit. The control circuit is coupled to the control node and the switch circuit and arranged to generate a switch control signal according to the trigger signal, and the switch control signal controls a switch status of the switch circuit.

Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a carrier having a first surface and including a power layer adjacent to the first surface of the carrier, an electrical component disposed on the first surface of the carrier, and a conductive element disposed on the first surface of the carrier. The electrical component is electrically connected to the power layer. The conductive element is electrically connected to the power layer. The conductive element, the power layer, and the electrical component form a power-transmission path.

Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.

Abstract: A device is disclosed that includes a control circuit and a scope circuit. The control circuit is configured to delay a voltage signal to generate a first control signal. The scope circuit is configured to be operated in one of a first mode and a second mode according to the first control signal. In the first mode, the scope circuit is configured to generate a first current signal indicating amplitudes of the voltage signal, and in the second mode, the scope circuit is configured to stop generating the first current signal.

Abstract: A compound semiconductor film structure includes a substrate, a first compound semiconductor epitaxial layer and a second compound semiconductor epitaxial layer. The substrate has a top surface. The first compound semiconductor epitaxial layer is formed on the top surface and has an epitaxial interface and at least one recess, wherein the epitaxial interface is disposed on one side of the first compound semiconductor epitaxial layer opposite to the side of the first compound semiconductor epitaxial layer facing the top surface, and the at least one recess is formed in the first compound semiconductor epitaxial layer. The second compound semiconductor epitaxial layer formed on the epitaxial interface. The top surface and the bottom of recess are separated by a distance substantially ranging between 0.8 ?m and 1.3 ?m.

Abstract: A semiconductor device is disclosed. In one example, the semiconductor device includes: an electronic component having a top surface, a bottom surface, and two end portions; a plurality of contacts disposed on the top surface; and a plurality of metal nodes disposed on the plurality of contacts. The plurality of contacts includes two end contacts disposed at the two end portions respectively and at least one intermediate contact disposed between the two end contacts. The plurality of metal nodes includes two end metal nodes disposed on the two end contacts respectively and at least one intermediate metal node disposed on the at least one intermediate contact.

Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.