Abstract: A sun visor for an automobile window is formed integrally and has a shape matching that of the upper edge of an automobile window frame. The sun visor has an upper edge and two sides formed with a smooth combining portion, a bulgy and arc-shaped screening portion formed to extend downward from a lower section of the combining portion, and a glue sheet adhered on an inner side of the combining portion. A decorative bar is installed on the outer side of the combining portion and has opposite ends respectively covered with a protective member that has an inner side formed with an engage groove for receiving each end of the decorative bar and an upper edge formed with a stop surface resisting against the top edge of both the decorative bar and the combining portion. The decorative bar functions to beautify the external look of the sun visor.

Abstract: A dynamic RAM which includes a first inverter, a second inverter, a sense amplifier, a first pair of switches, a pair of bit lines, and a dynamic RAM cell. The first inverter receives a first driving signal. A power end of the first inverter is coupled to a first voltage source. The second inverter receives a second driving signal output from the first inverter. A power end of the second inverter is coupled to a second voltage source. The sense amplifier senses and amplifies a voltage difference between a first sensing signal and a second sensing signal. A power end of the sense amplifier is coupled to a third voltage source, wherein a voltage value of the second voltage source is between a voltage value of the first voltage source and a voltage value of the third voltage source.

Abstract: This invention features a method of producing a triglyceride solution. The method includes contacting a liquid fatty acid alkyl ester and a substance containing triglyceride so that the triglyceride is dissolved into the fatty acid alkyl ester to form a triglyceride solution.

Abstract: A voltage converter including a first transistor, a second transistor, an inductor and a control module is provided. The first transistor has a source terminal receiving an input signal, and a body terminal receiving a first bias voltage. The second transistor has a drain terminal coupled to a drain terminal of the first transistor, a source terminal coupled to ground, and a body terminal receiving a second bias voltage. The inductor has a first terminal coupled to the drain terminal of the first terminal and a second terminal generating an output voltage. The control module is coupled to a gate terminal of the first transistor and a gate terminal of the second transistor for controlling conducting states of the first transistor and the second transistor.

Abstract: A method for operating a memory device with pseudo double clock signals comprises the steps of: generating an even clock signal and an odd clock signal, wherein the clock rates of both the even clock signal and the odd clock signal are half that of the input clock signal, and the even clock signal is the inverse signal of the odd clock signal; if the logic level of the even clock signal is 1 when receiving a trigger of a control signal, applying the even clock signal to a memory device; and if the logic level of the odd clock signal is 1 when receiving another trigger of the control signal, applying the odd clock signal to the memory device.

Abstract: An adaptive equalization apparatus is provided. The adaptive equalization apparatus includes an equalizer, a monitor circuit, and a control circuit. The equalizer receives a first signal, and equalizes the first signal according to an equalization parameter setting to thereby generate a second signal. The monitor circuit is electrically connected to the equalizer, and monitors edges of the second signal in a real-time manner to thereby generate a detection result. The control logic is electrically connected to the equalizer, and adaptively adjusts the equalization parameter setting according to the detection result.

Abstract: A memory device is provided. The memory device includes a plurality of memory array banks, a bus, a data buffer, and four data paths. The data buffer provides data from the memory array banks to an external node. The first data path includes a first compression module for compressing the data from the memory array banks to the bus. The second data path transmits the data from the memory array banks to the bus. The third data path includes a second compression module for compressing data from the bus to the data buffer. The fourth data path transmits the data from the bus to the data buffer.

Abstract: The present invention provides an apparatus and method that increases the utilization by processors on shared resources. It provides the minimum latency in a multiprocessor system during usage right exchange between multi-processors on a shared resource. The apparatus provides a timed mailbox including a timer. The timed mailbox is at least associated with a first processor and a second processor. The second processor starts to utilize a shared resource to perform a task. According to a predetermined clock cycle number, the timed mailbox issues a signal in advance to notify the first processor of the availability of the shared resource to be utilized by the first processor.

Abstract: A light-emitting device driving circuit and a method thereof are provided. A terminal of a light-emitting device is coupled to a supply voltage and a cathode of a diode via an inductor, and the other terminal is coupled to an anode of the diode. The light-emitting device driving circuit includes a switch, a current-sensing circuit, and a switch control circuit. The current-sensing circuit is coupled to the anode of the diode via the switch to determine whether or not to generate a turning-off control signal according to a conducting-current value of the switch. The switch control circuit controls an on/off state of the switch, and turns off the switch according to the turning-off control signal. Besides, the switch control circuit compares the conducting-current value with a reference-current value to generate a comparing result to dynamically adjust a time length of turning off the switch accordingly.

Abstract: A sampling rate allocation method for a wireless sensor network is provided. In this method, a distributed computing method is adopted to allow each node to calculate and obtain its decision table and energy table and upload its energy table to its parent node, and finally, the number of samples to be provided by all the child nodes is determined according to the decision table of the root node and a total sample number. Compared to the conventional techniques, the present invention provides a wireless sensor network which has longer life time and can meet the requirements to both the total number of samples and the fairness.

Abstract: A semiconductor memory device comprises a plurality of memory cells, a bit line sense amplifier, a local sense amplifier, and a sense amplifier. The memory cells are connected between a word line and a bit line pair, and the bit line sense amplifier is configured to amplify voltages of data from the bit line pair and then transmits the data to a local data line pair. The local sense amplifier is configured to amplify voltages of the data from the local data line pair and transmit the data to a global data line pair in response to first and second control signals, and the sense amplifier is configured to amplify the voltages of the data from the global data line pair and transmit the data to an input/output line pair during a read operation. The local sense amplifier comprises a first read circuit, a second read circuit, and a write circuit, and when the memory device performs the read operation, the data is transmitted from the first read circuit to the write circuit via the second read circuit.

Abstract: This invention relates to an oil degumming method that is free of emulsification. This method includes the steps of treating crude oil first with immobilized phospholipase and then extracting the phospholipase-treated crude oil with pure water or an aqueous solution.

Abstract: This invention relates to a method for producing an alkyl ester via a transesterification or esterification reaction. The method includes (1) mixing an oil source containing a triglyceride or a carboxylic acid and a first primary alcohol or a first secondary alcohol in a first organic solvent to form a first solution; in which each molecule of the first organic solvent contains 4-8 carbon atoms and a heteroatom; (2) reacting the triglyceride or the carboxylic acid with the first primary alcohol or the first secondary alcohol in the presence of a first lipase to produce a first alkyl ester, in which the first solution does not undergo phase separation throughout the reaction; and (3) separating the first alkyl ester from the first solution.

Abstract: A spindle motor includes a base plate, a stator, and a rotor. The base plate has a plurality of air-guiding holes. The stator includes a bearing portion and a plurality of coil portions. The bearing portion is fixed on the base plate. The coil portions are connected to and surrounded the bearing portion, and are disposed above the air-guiding holes. The rotor is rotatably mounted to the bearing portion and disposed adjacent the coil portions.

Abstract: An audio playing method is provided. The method includes: accessing an audio file from a data storage; transmitting the audio file to a decoder to decode and outputting the decoded audio file through the audio output unit; determining whether a skipping command is received from an input unit; determining the desired section according to the received skipping command if the skipping command is received from the input unit; accessing the starting address of the desired section from the control part, and playing the main audio part from the starting address.

Abstract: The invention provides a test circuit for n input/output arrays. Each of the n input/output arrays has M pairs of input/output. The test circuit includes M write drivers and M comparing circuits. The ith write driver provides an ith test signal to the ith inputs of all of the n input/output arrays, and 1?i?M. The jth comparing circuit determines if jth output signals of all of the n input/output arrays are the same, and outputs a jth comparing result correspondingly, and 1?j?M. The invention also provides a method of testing n input/output arrays. The invention also provides a storage device.

Abstract: A dynamic RAM which includes a first inverter, a second inverter, a sense amplifier, a first pair of switches, a pair of bit lines, and a dynamic RAM cell. The first inverter receives a first driving signal. A power end of the first inverter is coupled to a first voltage source. The second inverter receives a second driving signal output from the first inverter. A power end of the second inverter is coupled to a second voltage source. The sense amplifier senses and amplifies a voltage difference between a first sensing signal and a second sensing signal. A power end of the sense amplifier is coupled to a third voltage source, wherein a voltage value of the second voltage source is between a voltage value of the first voltage source and a voltage value of the third voltage source.

Abstract: A duty cycle correction circuit comprises first and second pulse generators, a clock dividing unit, a detecting unit, and a pulse width control unit. The first pulse generator is configured to generate a first edge of a first pulse signal in synchronization with a first edge of a first clock signal, and the second pulse generator is configured to generate a first edge of a second pulse signal in synchronization with a second edge of the first pulse signal. The clock dividing unit is configured to generate a second clock signal by dividing the frequency of the first clock signal. The detecting unit is configured to generate a detecting signal according to the second clock signal and a time interval between the first edge of the first pulse signal and a second edge of the second pulse signal. In particular, pulse widths of the first and second pulse signals are the same and are adjustable according to a control signal from the pulse width control unit.

Abstract: A method comprises simultaneously writing a test bit to a plurality of memory cells in the selected sections of a memory array corresponding to column address signals; individually and successively reading output bits from the memory cells in one of the selected sections of a designated row of the memory array corresponding to column address signals and row address signals; and error-checking the output bits with the test bit, wherein the memory array comprises the plurality of memory cells arranged in rows and columns and the memory cells of each row are divided into a plurality of sections.

Abstract: A duty cycle correction circuit comprises first and second pulse generators, a clock dividing unit, a detecting unit, and a pulse width control unit. The first pulse generator is configured to generate a first edge of a first pulse signal in synchronization with a first edge of a first clock signal, and the second pulse generator is configured to generate a first edge of a second pulse signal in synchronization with a second edge of the first pulse signal. The clock dividing unit is configured to generate a second clock signal by dividing the frequency of the first clock signal. The detecting unit is configured to generate a detecting signal according to the second clock signal and a time interval between the first edge of the first pulse signal and a second edge of the second pulse signal. In particular, pulse widths of the first and second pulse signals are the same and are adjustable according to a control signal from the pulse width control unit.