Abstract: A semiconductor memory device comprises a plurality of memory cells, a bit line sense amplifier, a local sense amplifier, and a sense amplifier. The memory cells are connected between a word line and a bit line pair, and the bit line sense amplifier is configured to amplify voltages of data from the bit line pair and then transmits the data to a local data line pair. The local sense amplifier is configured to amplify voltages of the data from the local data line pair and transmit the data to a global data line pair in response to first and second control signals, and the sense amplifier is configured to amplify the voltages of the data from the global data line pair and transmit the data to an input/output line pair during a read operation. The local sense amplifier comprises a first read circuit, a second read circuit, and a write circuit, and when the memory device performs the read operation, the data is transmitted from the first read circuit to the write circuit via the second read circuit.

Abstract: A main word line driving circuit for driving word lines in a memory device comprises first and second level shifting units and an inverting unit. The first level shifting unit is configured to convert a decode signal into a first operative signal, and the second level shifting unit is configured to convert the decode signal into a second operative signal. The inverting unit is configured to receive the first and second operative signals. A supply voltage of the first level shifting unit is selectively switched to a first bias voltage when the plurality of word lines are selected or partially selected and switched the output voltage to a second bias voltage when the plurality of word lines are deselected.

Abstract: A method for operating a memory device with pseudo double clock signals comprises the steps of: generating an even clock signal and an odd clock signal, wherein the clock rates of both the even clock signal and the odd clock signal are half that of the input clock signal, and the even clock signal is the inverse signal of the odd clock signal; if the logic level of the even clock signal is 1 when receiving a trigger of a control signal, applying the even clock signal to a memory device; and if the logic level of the odd clock signal is 1 when receiving another trigger of the control signal, applying the odd clock signal to the memory device.

Abstract: A memory device is provided. The memory device includes a plurality of memory array banks, a bus, a data buffer, and four data paths. The data buffer provides data from the memory array banks to an external node. The first data path includes a first compression module for compressing the data from the memory array banks to the bus. The second data path transmits the data from the memory array banks to the bus. The third data path includes a second compression module for compressing data from the bus to the data buffer. The fourth data path transmits the data from the bus to the data buffer.

Abstract: A multifunctional output driver capable of transmitting signals of different interfaces in different modes is provided, in which first and second current sources are provided, and first to fourth switching devices are coupled between the first and second current sources, and the first and second current source and the first to the fourth switching devices act as a current steering circuit. In a first transmission mode, the first and second switching devices are turned off, and the third and fourth switching devices and the first current source act as a current mode logic circuit to provide an output signal compatible with a first transmission interface according to an input signal from a pre-driver. In a second transmission mode, the current steering circuit outputs an output signal compatible with a second transmission interface according to the input signal from the pre-driver.

Abstract: A constant-current driving circuit includes a first current source, a reference voltage generating circuit and an output signal generating circuit. A terminal of the first current source is coupled to a terminal of a first LED string, wherein the terminal of the first current source has a first voltage. The reference voltage generating circuit is used for generating a reference voltage and comparing the first voltage with a first predetermined voltage to generate a first comparing signal to thereby adjust the reference voltage. The output signal generating circuit is used for outputting an output signal to another terminal of the first LED string and receiving the input signal, wherein the output signal generating circuit decides whether or not to output the input signal serving as the output signal according to the comparison result of the reference voltage with the second voltage.

Abstract: A voltage converting apparatus is disclosed. The voltage converting apparatus mentioned above includes an error comparator. The error comparator receives a feedback voltage and a reference voltage and generates a control signal according to the feedback voltage and the reference voltage. Moreover, the error comparator includes a differential pair, a first current source, and an offset voltage controlling circuit. The offset voltage controlling circuit receives a ramp enabling signal and adjusts a bias current flowing through at least one of a first and a second output terminal of the differential pair according to the ramp enabling signal.

Abstract: A delay circuit has: an inverting receiver with a resistive element, the inverting receiver having an input node for receiving an input signal and an output node coupled to the resistive element; a capacitive element, coupled to the output node of the inverting receiver and the resistive element; a first transistor, having lower turned ON voltage at higher temperature; a second transistor, used for generating a rail to rail signals on a terminal of the first transistor; and an output inverter, having an input node coupled to the first transistor and an output node for outputting an output signal of the delay circuit. Further, a third transistor is used for enhancing pulling low of the output signal of the delay circuit.

Abstract: A computer system and a method indicate the presence of a display output device. The method includes detecting whether the computer system has a display output or not. If detected, the display output device is selected according to the setting of a BIOS, and an indicator signals an indication to notify a user.

Abstract: The present invention relates to an improved wireless multiuser touch control system which comprises comprising an input end and a host control display end, wherein the input end comprises an input end and a host control display end. The input end has a plurality of touch control handwriting devices adopted for users to write characters and draft drawings on each of first touch screens thereof, respectively; and the host control display end has a computer mainframe and a host touch control display device. One user can write characters and draft drawings on a first touch screen of the touch control handwriting device by directly using the figures thereof, so that the characters and the drawings are simultaneously shown in the host touch control display device and the other touch control handwriting devices, so as to achieve an interactive multi-user discussion, meeting and teaching.

Abstract: A soft display system including: a soft display panel composed of a transparent substrate layer, a soft circuit layer and a display layer; a controller having a signal transmission device connected to the soft circuit layer; an input control device for making the soft circuit layer of the soft display panel generate signals corresponding characters or drawings; and a computer equipment having a computer application interface connected to the signal transmission device. The signals generated by the soft circuit layer are processed by the computer equipment. Then, by means of the conversion of the computer application interface, via the signal transmission device, the signals are output to the soft circuit layer. The images of the characters or drawings are shown on the display layer of the soft display panel.

Abstract: A multifunctional output driver capable of transmitting signals of different interfaces in different modes is provided, in which first and second current sources are provided, and first to fourth switching devices are coupled between the first and second current sources, and the first and second current source and the first to the fourth switching devices act as a current steering circuit. In a first transmission mode, the first and second switching devices are turned off, and the third and fourth switching devices and the first current source act as a current mode logic circuit to provide an output signal compatible with a first transmission interface according to an input signal from a pre-driver. In a second transmission mode, the current steering circuit outputs an output signal compatible with a second transmission interface according to the input signal from the pre-driver.

Abstract: A system configured for parking management in a parking facility, the system comprising a plurality of parking spaces, and a plurality of sensor units corresponding to the plurality of parking spaces, each of the plurality of sensor units being configured to detect a parking status of a corresponding one of the plurality of parking spaces and transmit a first message including the parking status of the corresponding one parking space in a wireless communication network.

Abstract: A tray of an optical disc drive for loading an optical disc in and out of the optical disc drive includes a depression for disposing the optical disc, a hollow space for providing a space for an optical pickup to access data while the optical pickup moves along a radial direction of the optical disc, a depressed portion formed at the middle portion of a rear end of the tray, and a reinforcement means formed of rigid material and disposed at the depressed portion for enhancing rigidity of the tray. The depression and depressed portion are monolithically formed.

Abstract: A low temperature coefficient oscillator including a current generator, a first and a second voltage generator, an amplifier, a resistor, a switch, a capacitor and an oscillating unit is provided. The current generator generates a first through a fourth current according to a control signal. The first voltage generator generates a first voltage according to the first current. The second voltage generator generates a second voltage according to the second current and a frequency signal. The amplifier generates the control signal according the first and second voltages. The resistor is coupled between a first terminal of the switch and ground, and a first terminal thereof receives the third current. The switch is conducted or not according the frequency signal. The capacitor is coupled between a second terminal of the switch and ground. The oscillating unit generates the frequency signal according to the fourth current and a voltage of the capacitor.

Abstract: A transmitter circuit, a receiver circuit and an interface switching module for SATA or SAS interface are provided. The invention uses transistors as elements with different impedance and also provides impedance modulating method in coordination with the exterior circuit and the layout design so as to develop an auto-switching mechanism between SATA and SAS interfaces, thereby integrating two transmission interfaces in a single system.

Abstract: A voltage converter including a first transistor, a second transistor, an inductor and a control module is provided. The first transistor has a source terminal receiving an input signal, and a body terminal receiving a first bias voltage. The second transistor has a drain terminal coupled to a drain terminal of the first transistor, a source terminal coupled to ground, and a body terminal receiving a second bias voltage. The inductor has a first terminal coupled to the drain terminal of the first terminal and a second terminal generating an output voltage. The control module is coupled to a gate terminal of the first transistor and a gate terminal of the second transistor for controlling conducting states of the first transistor and the second transistor.

Abstract: An image calibration method includes: (a) sensing at least one target pixel of a sensing row from an effective pixel region of an image sensor to generate at least one target pixel value; (b) sensing at least one reference pixel of a shading region in the image sensor to generate a calibration value, wherein the reference pixel and the sensing row do not belong to the same row; and (c) referring to the calibration value to calibrate and output the target pixel value.

Abstract: The present invention discloses a method for manufacturing a silicon material with high purity, and the method comprises the following steps of: selecting high purity quartz as a raw material; cleaning and comminuting the quartz; choosing the particle size of the quartz between 20 mm and 80 mm by an optical analyzer; purifying the quartz; melting the quartz in a metallurgical furnace; proceeding carbothermal reduction and post-refining to the quartz so as to obtain liquid silicon; draining the liquid silicon into a ladle through a tap hole of the metallurgical furnace; removing impurities of the liquid silicon in the ladle by Moist reduction Gas Blowing and Slag Treating; pouring the liquid silicon into a casting area of a crystal growth furnace; proceeding Directional Solidification to the liquid silicon in the casting area so as to obtain a solid silicon material.

Abstract: A system and a method for preparing cycloalkanone are provided. The method includes the steps of: (a) oxidizing cycloalkane to form a mixture containing ketone, alcohol and unreacted cycloalkane; (b) adding to the mixture alkali metal hydroxide or alkali metal carbonate to form a first mixed solution; (c) separating the first mixed solution into a first organic phase solution and a first aqueous phase solution; and (d) extracting the first organic phase solution by water to obtain a second organic phase solution and a second aqueous phase solution; and (e) distilling the second organic phase to separate out cycloalkanone. The method performs phase separation after a mixing step, and then performs water extraction, thereby effectively lowering the contents of the metal salts in the organic phases. Compared with acid-water extraction, the method not only provides better cooling effects but also reduces equipment corrosion, and therefore has the advantage of decreasing the need for sewage treatments.