Patents by Inventor Chung-Hao Tsai

Chung-Hao Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10978382
    Abstract: In an embodiment, a device includes: a package component including: a first integrated circuit die; an encapsulant at least partially surrounding the first integrated circuit die; a redistribution structure on the encapsulant, the redistribution structure physically and electrically coupling the first integrated circuit die; a first module socket attached to the redistribution structure; an interposer attached to the redistribution structure adjacent the first module socket, the outermost extent of the interposer extending beyond the outermost extent of the redistribution structure; and an external connector attached to the interposer.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Hui Lai, Shu-Rong Chun, Kuo Lung Pan, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 10978781
    Abstract: An antenna comprises a first layer having a first redistribution layer, a feeding line, a ground connection element, and one or more antenna inputs. The antenna also comprises one or more intermediate layers over the first layer. The antenna further comprises a second layer having a second redistribution layer over the one or more intermediate layers. The antenna additionally comprises one or more through vias arranged to communicatively couple the second redistribution layer and the first redistribution layer. The antenna also comprises a short element. The antenna further comprises one or more radiator antennas within the one or more through vias, the one or more radiator antennas being in communication with the one or more antenna inputs by way of the feeding line.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shien Hsieh, Chung-Hao Tsai, Chuei-Tang Wang, Chen-Hua Yu
  • Publication number: 20210096310
    Abstract: A package assembly and a manufacturing method thereof are provided. The package assembly includes a first package component and an optical signal port disposed aside the first package component. The first package component includes a first die including an electronic integrated circuit, a first insulating encapsulation laterally covering the first die, a redistribution structure disposed on the first die and the first insulating encapsulation, and a second die including a photonic integrated circuit and electrically coupled to the first die through the redistribution structure. The optical signal port is optically coupled to an edge facet of the second die of the first package component.
    Type: Application
    Filed: May 26, 2020
    Publication date: April 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chieh Chang, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang
  • Patent number: 10962711
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a photonic die, an encapsulant and a wave guide structure. The photonic die includes a substrate and a dielectric layer. The substrate has a wave guide pattern. The dielectric layer is disposed over the substrate. The photonic die is encapsulated by the encapsulant. The wave guide structure spans over the front side of the photonic die and a top surface of the encapsulant, and penetrates the dielectric layer to be optically coupled with the wave guide pattern.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chieh Chang, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang
  • Publication number: 20210091059
    Abstract: A semiconductor package includes a first die; a first redistribution structure over the first die, the first redistribution structure being conterminous with the first die; a second die over the first die, a first portion of the first die extending beyond a lateral extent of the second die; a conductive pillar over the first portion of the first die and laterally adjacent to the second die, the conductive pillar electrically coupled to first die; a molding material around the first die, the second die, and the conductive pillar; and a second redistribution structure over the molding material, the second redistribution structure electrically coupled to the conductive pillar and the second die.
    Type: Application
    Filed: November 18, 2020
    Publication date: March 25, 2021
    Inventors: Yu-Chia Lai, Kuo Lung Pan, Hung-Yi Kuo, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20210082888
    Abstract: A package includes a first package and a second package over and bonded to the first package. The first package includes a first device die, and a first encapsulant encapsulating the first device die therein. The second package includes an Independent Passive Device (IPD) die, and a second encapsulant encapsulating the IPD die therein. The package further includes a power module over and bonded to the second package.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: Yu-Chia Lai, Cheng-Chieh Hsieh, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20210066242
    Abstract: A package includes a package substrate, an interposer over and bonded to the package substrate, a first wafer over and bonding to the interposer, and a second wafer over and bonding to the first wafer. The first wafer has independent passive device dies therein. The second wafer has active device dies therein.
    Type: Application
    Filed: March 2, 2020
    Publication date: March 4, 2021
    Inventors: Chen-Hua Yu, Kuo Lung Pan, Shu-Rong Chun, Chi-Hui Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu
  • Publication number: 20210066137
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.
    Type: Application
    Filed: July 10, 2020
    Publication date: March 4, 2021
    Inventors: Chung-Wei Hsu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Hou-Yu Chen, Ching-Wei Tsai, Chih-Hao Wang, Lung-Kun Chu, Mao-Lin Huang, Jia-Ni Yu
  • Publication number: 20210057346
    Abstract: A semiconductor package includes dies, a redistribution structure, a conductive structure and connectors. The conductive plate is electrically connected to contact pads of at least two dies and is disposed on redistribution structure. The conductive structure includes a conductive plate and a solder cover, and the conductive structure extend over the at least two dies. The connectors are disposed on the redistribution structure, and at least one connector includes a conductive pillar. The conductive plate is at same level height as conductive pillar. The vertical projection of the conductive plate falls on spans of the at least two dies.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang, Wei-Ting Chen, Chien-Hsun Chen, Shih-Ya Huang
  • Patent number: 10930628
    Abstract: A method includes forming multiple photonic devices in a semiconductor wafer, forming a v-shaped groove in a first side of the semiconductor wafer, forming an opening extending through the semiconductor wafer, forming multiple conductive features within the opening, wherein the conductive features extend from the first side of the semiconductor wafer to a second side of the semiconductor wafer, forming a polymer material over the v-shaped groove, depositing a molding material within the opening, wherein the multiple conductive features are separated by the molding material, after depositing the molding material, removing the polymer material to expose the v-shaped groove, and placing an optical fiber within the v-shaped groove.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chieh Chang, Chung-Hao Tsai, Chuei-Tang Wang, Hsing-Kuo Hsia, Chen-Hua Yu
  • Publication number: 20210043608
    Abstract: A method includes thinning a semiconductor substrate of a device die to reveal through-substrate vias that extend into the semiconductor substrate, and forming a first redistribution structure, which includes forming a first plurality of dielectric layers over the semiconductor substrate, and forming a first plurality of redistribution lines in the first plurality of dielectric layers. The first plurality of redistribution lines are electrically connected to the through-substrate vias. The method further includes placing a first memory die over the first redistribution structure, and forming a first plurality of metal posts over the first redistribution structure. The first plurality of metal posts are electrically connected to the first plurality of redistribution lines. The first memory die is encapsulated in a first encapsulant. A second plurality of redistribution lines are formed over, and electrically connected to, the first plurality of metal posts and the first memory die.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 11, 2021
    Inventors: Chen-Hua Yu, Chung-Hao Tsai, Chuei-Tang Wang
  • Patent number: 10916851
    Abstract: A mobile electronic device includes a ground plane, a first slot, a plurality of first inductive elements, a first antenna, a second antenna, a first signal source, and a second signal source. The first slot is disposed in the ground plane to form a first ground portion and a second ground portion separated from each other. The first inductive elements are respectively connected to the first ground portion and the second ground portion. The first antenna and the second antenna respectively receive a radio-frequency signal in a predetermined band. The first signal source is electrically connected between the first antenna and the first ground portion and receives the radio-frequency signal from the first antenna. The second signal source is electrically connected between the second antenna and the second ground portion and receives the radio-frequency signal from the second antenna.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: February 9, 2021
    Assignee: Acer Incorporated
    Inventors: Wan-Chu Wei, Hsieh-Chih Lin, Hsin-Wu Chiang, Pei-Chi Ma, Yu-Chia Chang, Pang-Chun Tsai, Chung-hao Huang
  • Publication number: 20210013140
    Abstract: A semiconductor structure including at least one integrated circuit component is provided. The at least one integrated circuit component includes a first semiconductor substrate and a second semiconductor substrate electrically coupled to the first semiconductor substrate, wherein the first semiconductor substrate and the second semiconductor substrate are bonded through a first hybrid bonding interface, and at least one of the first semiconductor substrate or the second semiconductor substrate includes at least one first embedded capacitor.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 14, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ting Chen, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang
  • Publication number: 20210013191
    Abstract: Provided are a package structure and a method of manufacturing the same. The package structure includes a die, a first passive device, a plurality of through insulator vias (TIVs), an encapsulant, and a plurality of conductive connectors. The die has a front side and a backside opposite to each other. The first passive device is disposed aside the die. The TIVs are disposed between the die and the first passive device. The encapsulant laterally encapsulates the TIVs, the first passive device, and the die. The conductive connectors are disposed on the backside of the die, wherein the conductive connectors are electrically connected to the die and the first passive device by a plurality of solders.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 14, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ya Huang, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang
  • Publication number: 20200411996
    Abstract: An antenna device includes a package, a radiating element, and a director. The package includes a radio frequency (RF) die and a molding compound in contact with a sidewall of the RF die. The radiating element is in the molding compound and electrically coupled to the RF die. The director is in the molding compound, wherein the radiating element is between the director and the RF die, and a top of the radiating element is substantially coplanar with a top of the director.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 31, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chuei-Tang WANG, Chung-Hao TSAI, Jeng-Shien HSIEH, Wei-Heng LIN, Kuo-Chung YEE, Chen-Hua YU
  • Patent number: 10879183
    Abstract: A device includes a redistribution structure, a semiconductor device on the redistribution structure, a top package over the semiconductor device, the top package including a second semiconductor device, a molding compound interposed between the redistribution structure and the top package, a set of through vias between and electrically connecting the top package to the redistribution structure, and an interconnect structure disposed within the molding compound and electrically connecting the top package to the redistribution structure, the interconnect structure including a substrate and a passive device formed in the substrate, wherein the interconnect structure is free of active devices.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu
  • Publication number: 20200402847
    Abstract: A method of forming a package structure includes: forming an inductor comprising a through-via over a carrier; placing a semiconductor device over the carrier; molding the semiconductor device and the through-via in a molding material; and forming a first redistribution layer on the molding material, wherein the inductor and the semiconductor device are electrically connected by the first redistribution layer.
    Type: Application
    Filed: August 29, 2020
    Publication date: December 24, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Lin CHEN, Chung-Hao TSAI, Jeng-Shien HSIEH, Chuei-Tang WANG, Chen-Hua YU, Chih-Yuan CHANG
  • Patent number: 10867938
    Abstract: A package structure includes a sub-package, a conductive structure, and at least one first antenna. The sub-package includes at least one chip. The conductive structure is bonded onto and electrically connected to the sub-package. The at least one first antenna has a vertical polarization and is electrically connected to the at least one chip, wherein the at least one first antenna is partially located in the sub-package, and the at least one first antenna is extended within the sub-package into the conductive structure.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Chun Tang, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang
  • Patent number: 10861823
    Abstract: A method for forming through vias comprises the steps of forming a dielectric layer over a package and forming an RDL over the dielectric layer, wherein forming the RDL includes the steps of forming a seed layer, forming a first patterned mask over the seed layer, and performing a first metal plating. The method further includes forming through vias on top of a first portion of the RDL, wherein forming the through vias includes forming a second patterned mask over the seed layer and the RDL, and performing a second metal plating. The method further includes attaching a chip to a second portion of the RDL, and encapsulating the chip and the through vias in an encapsulating material.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo Lung Pan, Wei Sen Chang, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu
  • Publication number: 20200381357
    Abstract: A semiconductor chip including a die substrate, a plurality of first bonding structures, a plurality of conductive elements, at least one integrated device, a plurality of conductive posts and a protection layer is provided. The first bonding structures are disposed on the die substrate. The conductive elements are disposed on the die substrate adjacent to the first bonding structures. The integrated device is disposed on the die substrate over the first bonding structures, wherein the integrated device includes a plurality of second bonding structures and a plurality of conductive pillars, and the second bonding structures are hybrid bonded to the first bonding structures. The conductive posts are disposed on the conductive elements and surrounding the integrated device. The protection layer is encapsulating the integrated device and the conductive posts.
    Type: Application
    Filed: August 17, 2020
    Publication date: December 3, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu, Wei-Ting Chen