Abstract: A semiconductor package includes electric integrated circuit dies, photoelectric integrated circuit dies, and an inter-chip waveguide. The electric integrated circuit dies are laterally encapsulated by a first insulating encapsulant. The photoelectric integrated circuit dies are laterally encapsulated by a second insulating encapsulant. Each one of photoelectric integrated circuit dies includes an optical input/output terminal. The inter-chip waveguide is disposed over the second insulating encapsulant, wherein the photoelectric integrated circuit dies are optically communicated with each other through the inter-chip waveguide.

Abstract: Optical devices are presented herein. In an embodiment, the optical devices comprise a first active layer of first optical components, a first metallization layer over the first active layer, a first capacitor located within the first metallization layer, a first bond layer over the first metallization layer, and a first semiconductor device bonded to the first bond layer.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a photonic die, an encapsulant and a wave guide structure. The photonic die includes: a substrate, having a wave guide pattern formed at front surface; and a dielectric layer, covering the front surface of the substrate, and having an opening overlapped with an end portion of the wave guide pattern. The encapsulant laterally encapsulates the photonic die. The wave guide structure lies on the encapsulant and the photonic die, and extends into the opening of the dielectric layer, to be optically coupled to the wave guide pattern.

Abstract: A three-dimensional integrated circuit stack comprises a first integrated circuit structure, a second integrated circuit structure bonding to the first integrated circuit structure, and a redistribution structure. The first integrated circuit structure comprises a first semiconductor device, a first buffer structure, a first interconnect structure, a first conductive via, and a first through via. The first semiconductor device is located between the first buffer structure and the first interconnect structure. The first conductive via is extending through the first buffer structure and in contact with the first semiconductor device. The first through via is extending from the first buffer structure to the first interconnect structure. The redistribution structure is disposed on the first buffer structure, electrically connected to the first semiconductor device through the first conductive via, and electrically connected to the first interconnect structure through the first through via.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a photonic die, an encapsulant and a wave guide structure. The photonic die includes: a substrate, having a wave guide pattern formed at front surface; and a dielectric layer, covering the front surface of the substrate, and having an opening overlapped with an end portion of the wave guide pattern. The encapsulant laterally encapsulates the photonic die. The wave guide structure lies on the encapsulant and the photonic die, and extends into the opening of the dielectric layer, to be optically coupled to the wave guide pattern.

Abstract: A quantum memory device includes: a waveguide configured to spatially confine paths of photons therein; a memory cell that includes a micro-ring resonator (MRR), a frequency tuner, and a quantum memory material portion, wherein the MRR includes a first segment that is parallel to a segment of the waveguide, wherein the frequency tuner is configured to modulate a photon resonance frequency in the MRR by modifying an effective refractive index within, or around, a second segment of the MRR, and wherein the quantum memory material portion includes a quantum memory material having a ground state and an excitation state that stores photons therein and located within or on a third segment of the MRR; and a control circuit configured to modulate the photon resonance wavelength in the MRR during a first step of a photon capture operation to match a predefined wavelength, and to generate captured photons in the MRR.

Abstract: A package structure and method for forming the same are provided. The package structure includes a substrate having a front-side surface and a back-side surface, and an electrical device formed over the front-side surface of a substrate. The package structure includes a dielectric layer formed below and in direct contact with the back-side surface of the substrate, and a first optical device formed in the dielectric layer. The package structure also includes a protective layer formed below or above the first optical device; and an electro-optic effect material layer formed in the protective layer.

Abstract: A package structure is provided, and includes an interposer, a control unit, a plurality of computing units, a signal transmission layer, and an electric-optical material. The control unit is bonded to the interposer. The computing units are disposed around and connected to the control unit. The signal transmission layer is formed in the control unit and the computing units. The electric-optical material is formed in the control unit and the computing units, and the electric-optical material overlaps the signal transmission layer.

Abstract: Semiconductor device includes light-emitting die and semiconductor package. Light emitting die includes substrate and first conductive pad. Substrate has emission region located at side surface. First conductive pad is located at bottom surface of substrate. Semiconductor package includes semiconductor-on-insulator substrate, interconnection structure, second conductive pad, and through semiconductor via. Semiconductor-on-insulator substrate has linear waveguide formed therein. Interconnection structure is disposed on semiconductor-on-insulator substrate. Edge coupler is embedded within interconnection structure and is connected to linear waveguide. Semiconductor-on-insulator substrate and interconnection structure include recess in which light-emitting die is disposed. Edge coupler is located close to sidewall of recess. Second conductive pad is located at bottom of recess. Through semiconductor via extends across semiconductor-on-insulator substrate to contact second conductive pad.

Abstract: A method of manufacturing an electronic apparatus is described. The electronic apparatus includes an integrated fan-out package, a dielectric housing, and a plurality of conductive patterns. The dielectric housing is covering the integrated fan-out package, wherein a gap or a first dielectric layer is in between the dielectric housing and the integrated fan-out package. The plurality of conductive patterns is located on a surface of the dielectric housing, wherein the plurality of conductive patterns is located in between the dielectric housing and the integrated fan-out package.

Abstract: Embodiments provide regulated power routing through various inactive features of a device. In one embodiment, such inactive features include a through via wall which can be formed in an encapsulating material of a die stack. In another embodiment, such inactive features include a heat dissipation features formed over the die stack. In another embodiment, such inactive features include dummy via blocks attached adjacent a die cube. Yet other embodiments may combine the features of these embodiments without limitation.

Abstract: A package structure and a formation method are provided. The method includes forming electrical devices over a substrate and forming an interconnect structure over front sides of the electrical devices. The method also includes thinning the substrate and forming backside through vias connecting to backsides of the electrical devices. The method also includes attaching a waveguide layer over backsides of the electrical devices and forming conductive vias through the waveguide layer and electrically connected to the backside through vias.

Abstract: A package structure and a formation method are provided. The method includes forming a capacitor element over a first chip structure and forming a dielectric layer over the capacitor element. The method also includes forming a conductive bonding structure in the dielectric layer. A top surface of the conductive bonding structure is substantially coplanar with a top surface of the dielectric layer. The conductive bonding structure penetrates through the capacitor element and is electrically connected to the capacitor element. The method further includes bonding a second chip structure to the dielectric layer and the conductive bonding structure through dielectric-to-dielectric bonding and metal-to-metal bonding.

Abstract: In an embodiment, a method includes: bonding a back side of a first memory device to a front side of a second memory device with dielectric-to-dielectric bonds and with metal-to-metal bonds; after the bonding, forming first conductive bumps through a first dielectric layer at a front side of the first memory device, the first conductive bumps raised from a major surface of the first dielectric layer; testing the first memory device and the second memory device using the first conductive bumps; and after the testing, attaching a logic device to the first conductive bumps with reflowable connectors.

Abstract: A package structure includes a semiconductor die, an antenna substrate structure, a redistribution layer. The semiconductor die laterally encapsulated by a first encapsulant. The antenna substrate structure disposed over the semiconductor die, wherein the antenna substrate structure includes a first type of antenna, and a second type of antenna disposed on a side of the antenna substrate structure facing away from the semiconductor die. The redistribution layer disposed between the semiconductor die and the antenna substrate structure. The semiconductor die, the first type of antenna, and the second type of antenna are electrically coupled through the redistribution layer. The polarization of radiation emitted by the first type of antenna is perpendicular to a polarization of radiation emitted by the second type of antenna.

Abstract: An electronic apparatus is provided. The electronic apparatus includes an integrated fan-out package, a dielectric housing, and a plurality of conductive patterns. The dielectric housing is covering the integrated fan-out package, wherein a gap or a first dielectric layer is in between the dielectric housing and the integrated fan-out package. The plurality of conductive patterns is located on a surface of the dielectric housing, wherein the plurality of conductive patterns is located in between the dielectric housing and the integrated fan-out package.

Abstract: A method includes thinning a semiconductor substrate of a device die to reveal through-substrate vias that extend into the semiconductor substrate, and forming a first redistribution structure, which includes forming a first plurality of dielectric layers over the semiconductor substrate, and forming a first plurality of redistribution lines in the first plurality of dielectric layers. The first plurality of redistribution lines are electrically connected to the through-substrate vias. The method further includes placing a first memory die over the first redistribution structure, and forming a first plurality of metal posts over the first redistribution structure. The first plurality of metal posts are electrically connected to the first plurality of redistribution lines. The first memory die is encapsulated in a first encapsulant. A second plurality of redistribution lines are formed over, and electrically connected to, the first plurality of metal posts and the first memory die.

Abstract: A photonic integrated circuit (PIC) with a first structure of a ordinary optical material is enhanced with a second structure of a nonlinear optical material. The second structure provides or enhances nonlinear optical effects within the PIC. The first structure and the second structure may be in distinct layers. The first structure may be directly over and in contact with the second structure. Alternatively, the first structure and the second structures may be evanescently coupled while being vertically separated by a layer of cladding material. Lateral spacing may be used in combination with vertically spacing to precisely control a degree coupling between the first structure and the second structure.

Abstract: A method includes forming a reconstructed wafer, which includes forming a redistribution structure over a carrier, bonding a first plurality of memory dies over the redistribution structure, bonding a plurality of bridge dies over the redistribution structure, and bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. Each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, four of the plurality of logic dies. A second plurality of memory dies are bonded over the plurality of logic dies. The plurality of logic dies form a first array, and the second plurality of memory dies form a second array.

Abstract: A method includes bonding a capacitor die to a device die. The device die includes a first semiconductor substrate, active devices at a surface of the first semiconductor substrate, a plurality of low-k dielectric layers, a first dielectric layer over and contacting a top low-k dielectric layer in the plurality of low-k dielectric layers, and a first plurality of bond pads in the first dielectric layer. The capacitor die includes a second dielectric layer bonding to the first dielectric layer, a second plurality of bond pads in the second dielectric layer and bonding to the first plurality of bond pads, and a capacitor electrically coupled to the second plurality of bond pads. After the capacitor die is bonded to the device die, an aluminum-containing pad is formed over the capacitor die and electrically coupled to the device die. A polymer layer is formed over the aluminum-containing pad.