Abstract: A package structure includes at least one integrated circuit component, an insulating encapsulation, and a redistribution structure. The at least one integrated circuit component includes a semiconductor substrate, an interconnection structure disposed on the semiconductor substrate, and signal terminals and power terminals located on and electrically connecting to the interconnection structure. The interconnection structure is located between the semiconductor substrate and the signal terminals and between the semiconductor substrate and the power terminals, and where a size of the signal terminals is less than a size of the power terminals. The insulating encapsulation encapsulates the at least one integrated circuit component. The redistribution structure is located on the insulating encapsulation and electrically connected to the at least one integrated circuit component.

Abstract: A package structure includes a first semiconductor die, a second semiconductor die, a redistribution circuit structure, and a semiconductor device. The redistribution circuit structure has a first surface and a second surface opposite to the first surface, where the first surface is in contact with the first semiconductor die and the second semiconductor die, and the redistribution circuit structure is disposed on and electrically connected to the first semiconductor die and the second semiconductor die. The redistribution circuit structure includes a recess extending from the second surface toward the first surface. The semiconductor device is located in the recess and electrically connected to the first semiconductor die and the second semiconductor die through the redistribution circuit structure.

Abstract: A package includes a substrate, an Under-Bump Metallurgy (UBM) penetrating through the substrate, a solder region over and contacting the UBM, and an interconnect structure underlying the substrate. The interconnect structure is electrically coupled to the solder region through the UBM. A device die is underlying and bonded to the interconnect structure. The device die is electrically coupled to the solder region through the UBM and the interconnect structure. An encapsulating material encapsulates the device die therein.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a photonic die, an encapsulant and a wave guide structure. The photonic die includes: a substrate, having a wave guide pattern formed at front surface; and a dielectric layer, covering the front surface of the substrate, and having an opening overlapped with an end portion of the wave guide pattern. The encapsulant laterally encapsulates the photonic die. The wave guide structure lies on the encapsulant and the photonic die, and extends into the opening of the dielectric layer, to be optically coupled to the wave guide pattern.

Abstract: A passive device module includes a first tier, a second tier and connective terminals. The first tier includes a first semiconductor chip and a first encapsulant. The first semiconductor chip has contact posts. The encapsulant encapsulates the first semiconductor chip. The second tier is disposed on the first tier, and includes a second semiconductor chip, through interlayer walls, and a second encapsulant. The through interlayer walls are locate beside and face sidewalls of the second semiconductor chip and are electrically connected to the contact posts. The second encapsulant encapsulates the second semiconductor chip and the through interlayer walls. The connective terminals are disposed over the second tier and are electrically connected to the first semiconductor chip via the through interlayer walls. The first and second semiconductor chips include passive devices.

Abstract: A package includes a memory stack attached to a logic device, the memory stack including first memory structures, a first redistribution layer over and electrically connected to the first memory structures, second memory structures on the first redistribution layer, a second redistribution layer over and electrically connected to the second memory structures, and first metal pillars on the first redistribution layer and adjacent the second memory structures, the first metal pillars electrically connecting the first redistribution layer and the second redistribution layer, wherein each first memory structure of the first memory structures includes a memory die comprising first contact pads and a peripheral circuitry die comprising second contact pads, wherein the first contact pads of the memory die are bonded to the second contact pads of the peripheral circuitry die.

Abstract: A semiconductor package includes dies, a redistribution structure, a conductive structure and connectors. The conductive plate is electrically connected to contact pads of at least two dies and is disposed on redistribution structure. The conductive structure includes a conductive plate and a solder cover, and the conductive structure extend over the at least two dies. The connectors are disposed on the redistribution structure, and at least one connector includes a conductive pillar. The conductive plate is at same level height as conductive pillar. The vertical projection of the conductive plate falls on spans of the at least two dies.

Abstract: A method includes forming multiple photonic devices in a semiconductor wafer, forming a v-shaped groove in a first side of the semiconductor wafer, forming an opening extending through the semiconductor wafer, forming multiple conductive features within the opening, wherein the conductive features extend from the first side of the semiconductor wafer to a second side of the semiconductor wafer, forming a polymer material over the v-shaped groove, depositing a molding material within the opening, wherein the multiple conductive features are separated by the molding material, after depositing the molding material, removing the polymer material to expose the v-shaped groove, and placing an optical fiber within the v-shaped groove.

Abstract: A semiconductor package includes electric integrated circuit dies, photoelectric integrated circuit dies, and an inter-chip waveguide. The electric integrated circuit dies are laterally encapsulated by a first insulating encapsulant. The photoelectric integrated circuit dies are laterally encapsulated by a second insulating encapsulant. Each one of photoelectric integrated circuit dies includes an optical input/output terminal. The inter-chip waveguide is disposed over the second insulating encapsulant, wherein the photoelectric integrated circuit dies are optically communicated with each other through the inter-chip waveguide.

Abstract: A method includes placing a device die and a pre-formed dielectric block over a first carrier, encapsulating the device die and the pre-formed dielectric block in an encapsulating material, grinding a top side of the encapsulating material to expose the top side of the pre-formed dielectric block, removing the carrier from the encapsulating material, the pre-formed dielectric block, and the device die to reveal a bottom side of the pre-formed dielectric block, and forming a ground panel, a feeding line, and a patch on the encapsulating material. The ground panel, the feeding line, the patch, and the pre-formed dielectric block form a patch antenna.

Abstract: Provided is a package structure including a first die; a plurality of through vias, aside the first die; a first encapsulant laterally encapsulating the first die and the plurality of through vias; a first redistribution layer (RDL) structure on first sides of the first die, plurality of through vias, and the first encapsulant; a second RDL structure on second sides of the first die, the plurality of through vias, and the first encapsulant; and a plurality of conductive connectors, electrically connected to the second RDL structure. Portions of the first RDL structure, the plurality of through vias, and the second RDL structure are electrically connected to each other and form a solenoid inductor laterally aside the first die.

Abstract: A memory module includes a first redistribution structure, a second redistribution structure, first semiconductor dies, second semiconductor dies, an encapsulant, through insulator vias and thermally conductive material. Second redistribution structure is stacked over first redistribution structure. First semiconductor dies are sandwiched between first redistribution structure and second redistribution structure and disposed side by side. Second semiconductor dies are disposed on the second redistribution structure. The encapsulant laterally wraps the second semiconductor dies. The through insulator vias are disposed among the first semiconductor dies, extending from the first redistribution structure to the second redistribution structure. The through insulator vias are electrically connected to the first redistribution structure and the second redistribution structure.

Abstract: A semiconductor package includes a redistribution structure, a memory wafer, semiconductor dies and conductive vias. The memory wafer, disposed over the redistribution structure, includes at least one memory die. The semiconductor dies are disposed side by side with respect to each other, between the memory wafer and the redistribution structure, and are electrically connected to the redistribution structure. The conductive vias electrically connect the at least one memory die with the redistribution structure. A semiconductor package includes a redistribution structure, a reconstructed wafer, and a heat sink. The reconstructed wafer is disposed on the redistribution structure. The reconstructed wafer includes logic dies and memory dies. The logic dies are electrically connected to the redistribution structure. The memory dies are electrically connected to the redistribution structure and vertically stacked with the logic dies. The heat sink is disposed on the reconstructed wafer.

Abstract: A memory module includes a first redistribution structure, a second redistribution structure, first semiconductor dies, second semiconductor dies, an encapsulant, through insulator vias and thermally conductive material. Second redistribution structure is stacked over first redistribution structure. First semiconductor dies are sandwiched between first redistribution structure and second redistribution structure and disposed side by side. Second semiconductor dies are disposed on the second redistribution structure. The encapsulant laterally wraps the second semiconductor dies. The through insulator vias are disposed among the first semiconductor dies, extending from the first redistribution structure to the second redistribution structure. The through insulator vias are electrically connected to the first redistribution structure and the second redistribution structure.

Abstract: An antenna comprises a first layer having a first redistribution layer, a feeding line, a ground connection element, and one or more antenna inputs. The antenna also comprises one or more intermediate layers over the first layer. The antenna further comprises a second layer having a second redistribution layer over the one or more intermediate layers. The antenna additionally comprises one or more through vias arranged to communicatively couple the second redistribution layer and the first redistribution layer. The antenna also comprises a short element. The antenna further comprises one or more radiator antennas within the one or more through vias, the one or more radiator antennas being in communication with the one or more antenna inputs by way of the feeding line.

Abstract: A package assembly and a manufacturing method thereof are provided. The package assembly includes a first package component and an optical signal port disposed aside the first package component. The first package component includes a first die including an electronic integrated circuit, a first insulating encapsulation laterally covering the first die, a redistribution structure disposed on the first die and the first insulating encapsulation, and a second die including a photonic integrated circuit and electrically coupled to the first die through the redistribution structure. The optical signal port is optically coupled to an edge facet of the second die of the first package component.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a photonic die, an encapsulant and a wave guide structure. The photonic die includes a substrate and a dielectric layer. The substrate has a wave guide pattern. The dielectric layer is disposed over the substrate. The photonic die is encapsulated by the encapsulant. The wave guide structure spans over the front side of the photonic die and a top surface of the encapsulant, and penetrates the dielectric layer to be optically coupled with the wave guide pattern.

Abstract: A semiconductor package includes dies, a redistribution structure, a conductive structure and connectors. The conductive plate is electrically connected to contact pads of at least two dies and is disposed on redistribution structure. The conductive structure includes a conductive plate and a solder cover, and the conductive structure extend over the at least two dies. The connectors are disposed on the redistribution structure, and at least one connector includes a conductive pillar. The conductive plate is at same level height as conductive pillar. The vertical projection of the conductive plate falls on spans of the at least two dies.

Abstract: A method includes forming multiple photonic devices in a semiconductor wafer, forming a v-shaped groove in a first side of the semiconductor wafer, forming an opening extending through the semiconductor wafer, forming multiple conductive features within the opening, wherein the conductive features extend from the first side of the semiconductor wafer to a second side of the semiconductor wafer, forming a polymer material over the v-shaped groove, depositing a molding material within the opening, wherein the multiple conductive features are separated by the molding material, after depositing the molding material, removing the polymer material to expose the v-shaped groove, and placing an optical fiber within the v-shaped groove.

Abstract: A method includes thinning a semiconductor substrate of a device die to reveal through-substrate vias that extend into the semiconductor substrate, and forming a first redistribution structure, which includes forming a first plurality of dielectric layers over the semiconductor substrate, and forming a first plurality of redistribution lines in the first plurality of dielectric layers. The first plurality of redistribution lines are electrically connected to the through-substrate vias. The method further includes placing a first memory die over the first redistribution structure, and forming a first plurality of metal posts over the first redistribution structure. The first plurality of metal posts are electrically connected to the first plurality of redistribution lines. The first memory die is encapsulated in a first encapsulant. A second plurality of redistribution lines are formed over, and electrically connected to, the first plurality of metal posts and the first memory die.