Abstract: A method includes forming a reconstructed wafer, which includes forming a redistribution structure over a carrier, bonding a first plurality of memory dies over the redistribution structure, bonding a plurality of bridge dies over the redistribution structure, and bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. Each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, four of the plurality of logic dies. A second plurality of memory dies are bonded over the plurality of logic dies. The plurality of logic dies form a first array, and the second plurality of memory dies form a second array.

Abstract: An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and at least one first through interlayer via. The first redistribution structure includes a dielectric layer, a feed line at least partially disposed on the dielectric layer and a signal enhancement layer covering the feed line, wherein the signal enhancement layer has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The at least one first TIV is embedded in the insulation encapsulation and the signal enhancement layer.

Abstract: In an embodiment, a method includes: bonding a back side of a first memory device to a front side of a second memory device with dielectric-to-dielectric bonds and with metal-to-metal bonds; after the bonding, forming first conductive bumps through a first dielectric layer at a front side of the first memory device, the first conductive bumps raised from a major surface of the first dielectric layer; testing the first memory device and the second memory device using the first conductive bumps; and after the testing, attaching a logic device to the first conductive bumps with reflowable connectors.

Abstract: In an embodiment, a method includes: bonding a back side of a first memory device to a front side of a second memory device with dielectric-to-dielectric bonds and with metal-to-metal bonds; after the bonding, forming first conductive bumps through a first dielectric layer at a front side of the first memory device, the first conductive bumps raised from a major surface of the first dielectric layer; testing the first memory device and the second memory device using the first conductive bumps; and after the testing, attaching a logic device to the first conductive bumps with reflowable connectors.

Abstract: A method includes forming multiple photonic devices in a semiconductor wafer, forming a v-shaped groove in a first side of the semiconductor wafer, forming an opening extending through the semiconductor wafer, forming multiple conductive features within the opening, wherein the conductive features extend from the first side of the semiconductor wafer to a second side of the semiconductor wafer, forming a polymer material over the v-shaped groove, depositing a molding material within the opening, wherein the multiple conductive features are separated by the molding material, after depositing the molding material, removing the polymer material to expose the v-shaped groove, and placing an optical fiber within the v-shaped groove.

Abstract: An integrated circuit structure includes a substrate, a metal ring penetrating through the substrate, a dielectric region encircled by the metal ring, and a through-via penetrating through the dielectric region. The dielectric region is in contact with the through-via and the metal ring.

Abstract: A package structure includes a semiconductor die, an antenna substrate structure, a redistribution layer. The semiconductor die laterally encapsulated by a first encapsulant. The antenna substrate structure disposed over the semiconductor die, wherein the antenna substrate structure includes a first type of antenna, and a second type of antenna disposed on a side of the antenna substrate structure facing away from the semiconductor die. The redistribution layer disposed between the semiconductor die and the antenna substrate structure. The semiconductor die, the first type of antenna, and the second type of antenna are electrically coupled through the redistribution layer. The polarization of radiation emitted by the first type of antenna is perpendicular to a polarization of radiation emitted by the second type of antenna.

Abstract: Embodiments provide regulated power routing through various inactive features of a device. In one embodiment, such inactive features include a through via wall which can be formed in an encapsulating material of a die stack. In another embodiment, such inactive features include a heat dissipation features formed over the die stack. In another embodiment, such inactive features include dummy via blocks attached adjacent a die cube. Yet other embodiments may combine the features of these embodiments without limitation.

Abstract: A method of manufacturing a package structure includes: forming a backside RDL structure on a carrier; forming TIVs on the backside RDL structure; mounting at least one passive device on the backside RDL structure, so that the at least one passive device is disposed between the TIVs; placing a die on the at least one passive device, so that the at least one passive device is vertically sandwiched between the die and the backside RDL structure; forming an encapsulant laterally encapsulating the die, the TIVs, and the at least one passive device; forming a front side RDL structure on a front side of the die, the TIVs, and the encapsulant; releasing the backside RDL structure from the carrier; and mounting a package on the backside RDL structure, wherein the package is electrically connected to the at least one passive device by conductive connectors and solders.

Abstract: A method includes forming multiple photonic devices in a semiconductor wafer, forming a v-shaped groove in a first side of the semiconductor wafer, forming an opening extending through the semiconductor wafer, forming multiple conductive features within the opening, wherein the conductive features extend from the first side of the semiconductor wafer to a second side of the semiconductor wafer, forming a polymer material over the v-shaped groove, depositing a molding material within the opening, wherein the multiple conductive features are separated by the molding material, after depositing the molding material, removing the polymer material to expose the v-shaped groove, and placing an optical fiber within the v-shaped groove.

Abstract: A semiconductor package is provided. The semiconductor package includes a first die and a second die bonded to the first die. An encapsulant laterally encapsulates the second die. Through vias are disposed in the encapsulant. An interconnect structure is disposed on the second die, the through vias and the encapsulant. A redistribution structure is disposed on the interconnect structure. An inductor is embedded in the redistribution structure and the interconnect structure, wherein the inductor includes a portion of a metallization pattern of the redistribution structure and a portion of a conductive pattern of the interconnect structure. The portion of the metallization pattern of the inductor is adjacent to and substantially overlapped with the portion of the conductive pattern of the inductor. A manufacturing method of a semiconductor package is also provided.

Abstract: A semiconductor package includes an integrated circuit (IC) structure, an insulating encapsulation laterally covering the IC structure, and a redistribution structure disposed on the insulating encapsulation and the IC structure. The redistribution structure is electrically connected to the IC structure. The IC structure includes a first die, a capacitor structure, a dielectric layer laterally covering the first die and the capacitor structure, and a second die disposed on the dielectric layer, the first die, and the capacitor structure. The second die interacts with the capacitor structure, where a bonding interface between the second die and the first die is substantially coplanar with a bonding interface between the second die and the dielectric layer. A manufacturing method of a semiconductor package is also provided.

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a carrier substrate, an integrated circuit (IC) die thermally coupled to the carrier substrate through a thermally conductive layer, an antenna pattern disposed over the carrier substrate and the IC die, a redistribution structure disposed between the antenna pattern and the IC die, and an underfill disposed below and thermally coupled to the carrier substrate. The antenna pattern is electrically coupled to the IC die.

Abstract: Semiconductor device includes light-emitting die and semiconductor package. Light emitting die includes substrate and first conductive pad. Substrate has emission region located at side surface. First conductive pad is located at bottom surface of substrate. Semiconductor package includes semiconductor-on-insulator substrate, interconnection structure, second conductive pad, and through semiconductor via. Semiconductor-on-insulator substrate has linear waveguide formed therein. Interconnection structure is disposed on semiconductor-on-insulator substrate. Edge coupler is embedded within interconnection structure and is connected to linear waveguide. Semiconductor-on-insulator substrate and interconnection structure include recess in which light-emitting die is disposed. Edge coupler is located close to sidewall of recess. Second conductive pad is located at bottom of recess. Through semiconductor via extends across semiconductor-on-insulator substrate to contact second conductive pad.

Abstract: A package structure includes a semiconductor die, an antenna substrate structure, and a redistribution layer. The semiconductor die is laterally wrapped by a first encapsulant. The antenna substrate structure is disposed over the semiconductor die, wherein the antenna substrate structure includes a circuit substrate and at least one antenna element inlaid in the circuit substrate. The redistribution layer is disposed between the semiconductor die and the antenna substrate structure, wherein the at least one antenna element is electrically connected with the semiconductor die through the circuit substrate and the redistribution layer. The at least one antenna element includes patch antennas.

Abstract: A package structure includes at least one integrated circuit component, an insulating encapsulation, and a redistribution structure. The at least one integrated circuit component includes a semiconductor substrate, an interconnection structure disposed on the semiconductor substrate, and signal terminals and power terminals located on and electrically connecting to the interconnection structure. The interconnection structure is located between the semiconductor substrate and the signal terminals and between the semiconductor substrate and the power terminals, and where a size of the signal terminals is less than a size of the power terminals. The insulating encapsulation encapsulates the at least one integrated circuit component. The redistribution structure is located on the insulating encapsulation and electrically connected to the at least one integrated circuit component.

Abstract: A method of forming a package structure includes: forming an inductor comprising a through-via over a carrier; placing a semiconductor device over the carrier; molding the semiconductor device and the through-via in a molding material; and forming a first redistribution layer on the molding material, wherein the inductor and the semiconductor device are electrically connected by the first redistribution layer.

Abstract: In an embodiment, a method includes: bonding a back side of a first memory device to a front side of a second memory device with dielectric-to-dielectric bonds and with metal-to-metal bonds; after the bonding, forming first conductive bumps through a first dielectric layer at a front side of the first memory device, the first conductive bumps raised from a major surface of the first dielectric layer; testing the first memory device and the second memory device using the first conductive bumps; and after the testing, attaching a logic device to the first conductive bumps with reflowable connectors.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a photonic die, an encapsulant and a wave guide structure. The photonic die includes: a substrate, having a wave guide pattern formed at front surface; and a dielectric layer, covering the front surface of the substrate, and having an opening overlapped with an end portion of the wave guide pattern. The encapsulant laterally encapsulates the photonic die. The wave guide structure lies on the encapsulant and the photonic die, and extends into the opening of the dielectric layer, to be optically coupled to the wave guide pattern.

Abstract: An antenna device includes a radio frequency (RF) die, a first dielectric layer, a feeding line, a ground line, a second dielectric layer, and a radiating element. The first dielectric layer is over the RF die. The feeding line is in the first dielectric layer and is connected to the RF die. The ground line is in the first dielectric layer and is spaced apart from the feeding line. The second dielectric layer covers the first dielectric layer. The radiating element is over the second dielectric layer and is not in physically contact with the feeding line.