Patents by Inventor Chung Hsien Lin
Chung Hsien Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8704317Abstract: A microelectromechanical system (MEMS) device includes a substrate and an oxide layer formed on the substrate. A cavity is etched in the oxide layer. A microstructure device layer is bonded to the oxide layer, over the cavity. The microstructure device layer includes a substantially solid microstructure MEMS device formed in the microstructure device layer and suspended over a portion of the cavity. An anchor is formed in the device layer and configured to support the microstructure device, the anchor having an undercut in the oxide layer. The undercut has a length along the anchor that is less than one-half a length of an outer boundary dimension of the microstructure MEMS device.Type: GrantFiled: December 20, 2012Date of Patent: April 22, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hsien Lin, Chun-Wen Cheng, Chia-Hua Chu, Yi Heng Tsai
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Publication number: 20140042562Abstract: A device includes a Micro-Electro-Mechanical System (MEMS) wafer having a MEMS device therein. The MEMS device includes a movable element, and first openings in the MEMS wafer. The movable element is disposed in the first openings. A carrier wafer is bonded to the MEMS wafer. The carrier wafer includes a second opening connected to the first openings, wherein the second opening includes an entry portion extending from a surface of the carrier wafer into the carrier wafer, and an inner portion wider than the entry portion, wherein the inner portion is deeper in the carrier wafer than the entry portion.Type: ApplicationFiled: August 9, 2012Publication date: February 13, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Hua Chu, Chun-Wen Cheng, Te-Hao Lee, Chung-Hsien Lin
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Patent number: 8648468Abstract: Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum -based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.Type: GrantFiled: July 29, 2010Date of Patent: February 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Richard Chu, Martin Liu, Chia-Hua Chu, Yuan-Chih Hsieh, Chung-Hsien Lin, Lan-Lin Chao, Chun-Wen Cheng, Mingo Liu
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Patent number: 8633554Abstract: The present disclosure provides a micro-electro-mechanical systems (MEMS) device and a method for fabricating such a device. In an embodiment, a MEMS device includes a substrate, a dielectric layer above the substrate, an etch stop layer above the dielectric layer, and two anchor plugs above the dielectric layer, the two anchor plugs each contacting the etch stop layer or a top metal layer disposed above the dielectric layer. The device further comprises a MEMS structure layer disposed above a cavity formed between the two anchor plugs and above the etch stop layer from release of a sacrificial layer.Type: GrantFiled: February 1, 2013Date of Patent: January 21, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Hua Chu, Yi Heng Tsai, Kai-Chih Liang, Chia-Pao Shu, Li-Cheng Chu, Kuei-Sung Chang, Hsueh-An Yang, Chung-Hsien Lin
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Patent number: 8629517Abstract: A method of wafer level packaging includes providing a substrate including a buried oxide layer and a top oxide layer, and etching the substrate to form openings above the buried oxide layer and a micro-electro-mechanical systems (MEMS) resonator element between the openings, the MEMS resonator element enclosed within the buried oxide layer, the top oxide layer, and sidewall oxide layers. The method further includes filling the openings with polysilicon to form polysilicon electrodes adjacent the MEMS resonator element, removing the top oxide layer and the sidewall oxide layers adjacent the MEMS resonator element, bonding the polysilicon electrodes to one of a complementary metal-oxide semiconductor (CMOS) wafer or a carrier wafer, removing the buried oxide layer adjacent the MEMS resonator element, and bonding the substrate to a capping wafer to seal the MEMS resonator element between the capping wafer and one of the CMOS wafer or the carrier wafer.Type: GrantFiled: December 10, 2012Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Wen Cheng, Chung-Hsien Lin, Chia-Hua Chu
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Publication number: 20130285170Abstract: A MEMS device is described. The device includes a micro-electro-mechanical systems (MEMS) substrate including a first bonding layer, a semiconductor substrate including a second bonding layer, and a cap including a third bonding layer, the cap coupled to the semiconductor substrate by bonding the second bonding layer to the third bonding layer. The first bonding layer includes silicon, the semiconductor substrate is electrically coupled to the MEMS substrate by bonding the first bonding layer to the second bonding layer, and the MEMS substrate is hermetically sealed between the cap and the semiconductor substrate.Type: ApplicationFiled: June 27, 2013Publication date: October 31, 2013Inventors: Chung-Hsien Lin, Chia-Hua Chu, Li-Cheng Chu, Yuan-Chih Hsieh, Chun-Wen Cheng
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Patent number: 8569808Abstract: A semiconductor device with temperature control system. Embodiments of the device may include a MEMS chip including a first heater with a dedicated first temperature control loop and a CMOS chip including a second heater with a dedicated second temperature control loop. Each control loop may have a dedicated temperature sensor for controlling the thermal output of each heater. The first heater and sensor are disposed proximate to a MEMS device in the MEMS chip for direct heating thereof. The temperature of the MEMS chip and CMOS chip are independently controllable of each other via the temperature control loops.Type: GrantFiled: April 6, 2012Date of Patent: October 29, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tung-Tsun Chen, Chia-Hua Chu, Chung-Hsien Lin, Jui-Cheng Huang
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Publication number: 20130264610Abstract: A semiconductor device with temperature control system. Embodiments of the device may include a MEMS chip including a first heater with a dedicated first temperature control loop and a CMOS chip including a second heater with a dedicated second temperature control loop. Each control loop may have a dedicated temperature sensor for controlling the thermal output of each heater. The first heater and sensor are disposed proximate to a MEMS device in the MEMS chip for direct heating thereof. The temperature of the MEMS chip and CMOS chip are independently controllable of each other via the temperature control loops.Type: ApplicationFiled: April 6, 2012Publication date: October 10, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tung-Tsun CHEN, Chia-Hua CHU, Chung-Hsien LIN, Jui-Cheng HUANG
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Patent number: 8551798Abstract: The present disclosure provides a microstructure device with an enhanced anchor and a narrow air gap. One embodiment of a microstructure device provided herein includes a layered wafer. The layered wafer includes a silicon handle layer, a buried oxide layer formed on the handle layer, and a silicon device layer formed on the buried oxide layer. A top oxide layer is formed on the device layer. The top oxide layer, the device layer, and the buried oxide layer are etched, thereby forming trenches to create an anchor and a microstructure device in the device layer. In process of fabricating the device, a thermal oxide layer is formed along sides of the microstructure device to enclose the microstructure device in the buried oxide layer, the top oxide layer and the thermal oxide layer. Then, a poly layer if formed to fill in the trenches and enclose the anchor. After the poly layer fills in the trenches, the oxide layers enclosing the microstructure device are etched away, releasing the microstructure device.Type: GrantFiled: September 21, 2010Date of Patent: October 8, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hsien Lin, Chia-Hua Chu, Chun-Wen Cheng
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Patent number: 8525278Abstract: A method and device having chip scale MEMS packaging is described. A first substrate includes a MEMS device and a second substrate includes an integrated circuit. The frontside of the first substrate is bonded to the backside of the second substrate. Thus, the second substrate provides a cavity to encase, protect or operate the MEMS device within. The bond may provide an electrical connection between the first and second substrate. In an embodiment, a through silicon via is used to carry the signals from the first substrate to an I/O connection on the frontside of the second substrate.Type: GrantFiled: August 19, 2011Date of Patent: September 3, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Hua Chu, Chung-Hsien Lin
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Publication number: 20130213139Abstract: A vacuum sensor for sensing vacuum in a sealed enclosure is provided. The sealed enclosure includes active MEMS devices desired to be maintained in vacuum conditions. The vacuum sensor includes a motion beam anchored to an internal surface in the sealed enclosure. A driving electrode is disposed beneath the motion beam and a bias is supplied to cause the motion beam to deflect through electromotive force. A sensing electrode is also provided and detects capacitance between the sensing electrode disposed on the internal surface, and the motion beam. Capacitance changes as the gap between the motion beam and the sensing electrode changes. The amount of deflection is determined by the vacuum level in the sealed enclosure. The vacuum level in the sealed enclosure is thereby sensed by the sensing electrode.Type: ApplicationFiled: February 21, 2012Publication date: August 22, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tung-Tsun CHEN, Jui-Cheng HUANG, Chung-Hsien LIN
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Patent number: 8486744Abstract: The present disclosure provides a method for fabricating a MEMS device including multiple bonding of substrates. In an embodiment, a method includes providing a micro-electro-mechanical systems (MEMS) substrate including a first bonding layer, providing a semiconductor substrate including a second bonding layer, and providing a cap including a third bonding layer. The method further includes bonding the MEMS substrate to the semiconductor substrate at the first and second bonding layers, and bonding the cap to the semiconductor substrate at the second and third bonding layers to hermetically seal the MEMS substrate between the cap and the semiconductor substrate. A MEMS device fabricated by the above method is also provided.Type: GrantFiled: September 28, 2010Date of Patent: July 16, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hsien Lin, Chia-Hua Chu, Li-Cheng Chu, Yuan-Chih Hsieh, Chun-Wen Cheng
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Publication number: 20130168852Abstract: A microelectromechanical system (MEMS) device may include a MEMS structure over a first substrate. The MEMS structure comprises a movable element. Depositing a first conductive material over the first substrate and etching trenches in a second substrate. Filling the trenches with a second conductive material and depositing a third conductive material over the second conductive material and the second substrate. Bonding the first substrate and the second substrate and thinning a backside of the second substrate which exposes the second conductive material in the trenches.Type: ApplicationFiled: August 9, 2012Publication date: July 4, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kai-Chih Liang, Chia-Hua Chu, Te-Hao Lee, Jiou-Kang Lee, Chung-Hsien Lin
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Patent number: 8455982Abstract: An integrated circuit device includes a semiconductor substrate having a device region and an alignment region. A first material layer is disposed over the semiconductor substrate, and includes a device feature in the device region and a dummy feature in the alignment region. A dimension of the dummy feature is less than a dimension of an alignment detector. A second material layer is disposed over the semiconductor substrate, and includes an alignment feature in the alignment region. The alignment feature disposed over the dummy feature.Type: GrantFiled: February 29, 2012Date of Patent: June 4, 2013Assignee: Taiwan Semiconductor Manufacturing Company, LtdInventors: Meng-Wei Chen, Chi-Chuang Lee, Chung-Hsien Lin
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Patent number: 8410665Abstract: The present disclosure provides a micro device. The device has a micro-electro-mechanical systems (MEMS) movable structure, a plurality of metal loops over the MEMS movable structure, and a piezoelectric element over the MEMS movable structure. Frontside and backside capping wafers are bonded to the MEMS structure, with the frontside and backside capping wafers encapsulating the MEMS movable structure, the plurality of metal loops, and the piezoelectric element. The device further includes a magnet disposed on the frontside capping wafer over the plurality of metal loops.Type: GrantFiled: December 23, 2010Date of Patent: April 2, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tien-Kan Chung, Chung-Hsien Lin, Yao-Te Huang, Chia-Hua Chu, Chia-Ming Hung, Wen-Chuan Tai, Chang-Yi Yang
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Publication number: 20130043547Abstract: A method and device having chip scale MEMS packaging is described. A first substrate includes a MEMS device and a second substrate includes an integrated circuit. The frontside of the first substrate is bonded to the backside of the second substrate. Thus, the second substrate provides a cavity to encase, protect or operate the MEMS device within. The bond may provide an electrical connection between the first and second substrate. In an embodiment, a through silicon via is used to carry the signals from the first substrate to an I/O connection on the frontside of the second substrate.Type: ApplicationFiled: August 19, 2011Publication date: February 21, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd. ("TSMC")Inventors: Chia-Hua Chu, Chung-Hsien Lin
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Patent number: 8368152Abstract: The present disclosure provides a micro-electro-mechanical systems (MEMS) device and a method for fabricating such a device. In an embodiment, a MEMS device includes a substrate, a dielectric layer above the substrate, an etch stop layer above the dielectric layer, and two anchor plugs above the dielectric layer, the two anchor plugs each contacting the etch stop layer or a top metal layer disposed above the dielectric layer. The device further comprises a MEMS structure layer disposed above a cavity formed between the two anchor plugs and above the etch stop layer from release of a sacrificial layer.Type: GrantFiled: April 18, 2011Date of Patent: February 5, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Hua Chu, Yi Heng Tsai, Kai-Chih Liang, Chia-Pao Shu, Li-Cheng Chu, Kuei-Sung Chang, Hsueh-An Yang, Chung-Hsien Lin
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Patent number: 8343789Abstract: The present disclosure provides a system of fabricating a microstructure device with an improved anchor. A method of fabricating a microstructure device with an improved anchor includes providing a substrate and forming an oxide layer on the substrate. Then, a cavity is etched in the oxide layer, such that the cavity includes a sidewall in the oxide layer. A microstructure device layer is then bonded to the oxide layer over the cavity. Forming a microstructure device, a trench is etched in the device layer to define an outer boundary of the microstructure device. In an embodiment, the outer boundary is substantially outside of the sidewall of the cavity. Then, the sidewall of the cavity is etched away through the trench in the device layer, to thereby suspend the microstructure device over the cavity.Type: GrantFiled: August 17, 2010Date of Patent: January 1, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hsien Lin, Chun-Wen Cheng, Chia-Hua Chu, Yi Heng Tsai
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Publication number: 20120313235Abstract: The present disclosure provides an embodiment of a micro-electro-mechanical system (MEMS) structure, the MEMS structure comprising a MEMS substrate; a first and second conductive plugs of a semiconductor material disposed on the MEMS substrate, wherein the first conductive plug is configured for electrical interconnection and the second conductive plug is configured as an anti-stiction bump; a MEMS device configured on the MEMS substrate and electrically coupled with the first conductive plug; and a cap substrate bonded to the MEMS substrate such that the MEMS device is enclosed therebetween.Type: ApplicationFiled: June 10, 2011Publication date: December 13, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Hua Chu, Kuei-Sung Chang, Chung-Hsien Lin
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Patent number: 8330559Abstract: A method of wafer level packaging includes providing a substrate including a buried oxide layer and a top oxide layer, and etching the substrate to form openings above the buried oxide layer and a micro-electro-mechanical systems (MEMS) resonator element between the openings, the MEMS resonator element enclosed within the buried oxide layer, the top oxide layer, and sidewall oxide layers. The method further includes filling the openings with polysilicon to form polysilicon electrodes adjacent the MEMS resonator element, removing the top oxide layer and the sidewall oxide layers adjacent the MEMS resonator element, bonding the polysilicon electrodes to one of a complementary metal-oxide semiconductor (CMOS) wafer or a carrier wafer, removing the buried oxide layer adjacent the MEMS resonator element, and bonding the substrate to a capping wafer to seal the MEMS resonator element between the capping wafer and one of the CMOS wafer or the carrier wafer.Type: GrantFiled: September 10, 2010Date of Patent: December 11, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Wen Cheng, Chung-Hsien Lin, Chia-Hua Chu