Patents by Inventor Chung-Hsing Wang

Chung-Hsing Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DIAGONAL TORUS NETWORK
    Publication number: 20230066045
    Abstract: A device is disclosed that includes multiple channels and multiple processing nodes. Each processing node includes input/output (I/O) ports coupled to the channels and channel control modules coupled to the I/O ports. Each processing node is configured to select, by the channel control module in a first operation, a first I/O port of the I/O ports; communicate a first message, via the first I/O port, to a first processing node over a first channel or a second processing node over a second channel orthogonal to the first channel in a logic representation; select, by the channel control module in a second operation, a second I/O port of the I/O ports; and communicate a second message, via the second I/O port, to a third processing node over a third channel extending in a diagonal direction and non-orthogonal to the first and second channels in the logic representation.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jerry Chang Jui Kao, Huang-Yu Chen, Yung-Chen Chien, Tzu-Ying Lin, Wei-Hsiang Ma, Chung-Hsing Wang
  • Integrated circuit with thicker metal lines on lower metallization layer
    Patent number: 11593546
    Abstract: An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A total length of the second metal lines of the second net is shorter than a total length of the first metal lines of the first net. A count of the f first metal vias of the first net is less than a count of the second metal vias of the second net.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuang-Hung Chang, Yuan-Te Hou, Chung-Hsing Wang, Yung-Chin Hou
  • Method, system, and storage medium of resource planning for designing semiconductor device
    Patent number: 11574106
    Abstract: A method includes: accessing a design data of an integrated circuit (IC), wherein the design data includes a transistor layer and a plurality of metal layers over the transistor layer; assigning a bin size for each of the metal layers based on layout properties of the respective metal layers, wherein a bin size of a higher larger of the metal layers has a greater bin size than that of a lower layer of the metal layers; performing resource planning on the transistor layer and each of the metal layers according to the assigned bin sizes of the respective metal layers; and updating the design data according to the resource planning. At least one of the accessing, assigning, performing and updating steps is conducted by at least one processor.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: February 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yen-Hung Lin, Chung-Hsing Wang, Yuan-Te Hou
  • Block level design method for heterogeneous PG-structure cells
    Patent number: 11574108
    Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: February 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Hung Lin, Yuan-Te Hou, Chung-Hsing Wang
  • CONDUCTOR SCHEME SELECTION AND TRACK PLANNING FOR MIXED-DIAGONAL-MANHATTAN ROUTING
    Publication number: 20230023165
    Abstract: The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.
    Type: Application
    Filed: October 3, 2022
    Publication date: January 26, 2023
    Inventors: Sheng-Hsiung Chen, Huang-Yu Chen, Chung-Hsing Wang, Jerry Chang Jui Kao
  • Integrated circuit and method of generating integrated circuit layout
    Patent number: 11552068
    Abstract: A method includes forming a cell layer including first and second cells, each of which is configured to perform a circuit function; forming a first metal layer above the cell layer and including a first conductive feature and a second conductive feature extending along a first direction, in which the first conductive feature extends from the first cell into the second cell, and in which a shortest distance between a center line of the first conductive feature and a center line of the second conductive feature along a second direction is less than a width of the first conductive feature, and the second direction is perpendicular to the first direction; forming a first conductive via interconnecting the cell layer and the conductive feature.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: January 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fong-Yuan Chang, Kuo-Nan Yang, Chung-Hsing Wang, Lee-Chung Lu, Sheng-Fong Chen, Po-Hsiang Huang, Hiranmay Biswas, Sheng-Hsiung Chen, Aftab Alam Khan
  • LAYOUTS FOR CONDUCTIVE LAYERS IN INTEGRATED CIRCUITS
    Publication number: 20220406716
    Abstract: Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.
    Type: Application
    Filed: June 18, 2021
    Publication date: December 22, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yu LO, Chung-Hsing WANG, Chin-Shen LIN, Kuo-Nan YANG, Meng-Xiang LEE, Hao-Tien KAN, Jhih-Hong YE
  • Routing structure and method of forming the same
    Patent number: 11532562
    Abstract: The present disclosure provides a routing structure. The routing structure includes a substrate having a first circuit region and a boundary surrounding the first circuit region. The routing structure also includes a first conductive trace coupled to a first conductive pad disposed in the first circuit region. The first conductive trace is inclined with respect to the boundary of the substrate. A method of forming a routing structure is also disclosed.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chin-Shen Lin, Wan-Yu Lo, Meng-Xiang Lee, Hao-Tien Kan, Kuo-Nan Yang, Chung-Hsing Wang
  • CONDUCTOR SCHEME SELECTION AND TRACK PLANNING FOR MIXED-DIAGONAL-MANHATTAN ROUTING
    Publication number: 20220382958
    Abstract: The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.
    Type: Application
    Filed: May 27, 2021
    Publication date: December 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Hsiung Chen, Huang-Yu Chen, Chung-Hsing Wang, Jerry Chang Jui Kao
  • Integrated Circuit Having a High Cell Density
    Publication number: 20220367358
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Conductor scheme selection and track planning for mixed-diagonal-Manhattan routing
    Patent number: 11501052
    Abstract: The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: November 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Sheng-Hsiung Chen, Huang-Yu Chen, Chung-Hsing Wang, Jerry Chang Jui Kao
  • INTEGRATED CIRCUIT DEVICE AND METHOD
    Publication number: 20220359491
    Abstract: An integrated circuit (IC) device includes a substrate, and a cell over the substrate. The cell includes at least one active region and at least one gate region extending across the at least one active region. The cell further includes at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to external circuitry outside the cell. The at least one IO pattern extends obliquely to both the at least one active region and the at least one gate region.
    Type: Application
    Filed: May 6, 2021
    Publication date: November 10, 2022
    Inventors: Wei-Ren CHEN, Cheng-Yu LIN, Hui-Zhong ZHUANG, Yung-Chen CHIEN, Jerry Chang Jui KAO, Huang-Yu CHEN, Chung-Hsing WANG
  • METHOD FOR EVALUATING FAILURE-IN-TIME
    Publication number: 20220309224
    Abstract: Failure-in-time (FIT) evaluation methods for an IC are provided. Data representing a layout of the IC is accessed, and the layout includes a metal line and a plurality of vertical interconnect accesses (VIAs). The metal line is divided into a first sub-line with a first line width and a second sub-line with a second line width. A plurality of nodes are picked along the first and second sub-lines of the metal line. The metal line is divided into a plurality of metal segments based on the nodes. FIT value is determined for each of the metal segments to verify the layout and fabricate the IC. The first line width is greater than the second line width.
    Type: Application
    Filed: June 15, 2022
    Publication date: September 29, 2022
    Inventors: Chin-Shen LIN, Ming-Hsien LIN, Kuo-Nan YANG, Chung-Hsing WANG
  • METHOD OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING STANDARD-CELL-ADAPTED POWER GRID ARRANGEMENT
    Publication number: 20220292247
    Abstract: A method (of fabricating a power grid (PG) arrangement in a semiconductor) includes: forming a first layer including conductive lines (C_1st lines)which include interspersed alpha C_1st lines and beta C_1st lines designated correspondingly for first and second reference voltages; and forming a second layer over the first layer, the second layer including segments (C_2nd segments) which include interspersed alpha C_2nd segments and beta C_2nd segments designated correspondingly for the first and second reference voltages; and, relative to the first direction, each beta C_2nd segment being substantially asymmetrically between corresponding adjacent ones of the alpha C_2nd segments.
    Type: Application
    Filed: May 31, 2022
    Publication date: September 15, 2022
    Inventors: Hiranmay BISWAS, Chung-Hsing WANG, Chin-Shen LIN, Kuo-Nan YANG
  • SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING
    Publication number: 20220285263
    Abstract: A method of forming a semiconductor arrangement includes forming a first capacitor in a first voltage domain and forming a second capacitor in the first voltage domain. The first capacitor is connected in parallel with the second capacitor. A third capacitor and a fourth capacitor are formed in a second voltage domain. The third capacitor is connected in series with the fourth capacitor. The first capacitor and the second capacitor are connected in parallel with a supply terminal of the first voltage domain and a reference terminal of the first voltage domain. The fourth capacitor is connected to a supply terminal of the second voltage domain. The third capacitor is connected to a reference terminal of the second voltage domain.
    Type: Application
    Filed: June 1, 2021
    Publication date: September 8, 2022
    Inventors: Wan-Yu Lo, Chung-Hsing Wang, Chin-Shen Lin, Kuo-Nan Yang, Hsiang-Ku Shen, Dian-Hau Chen
  • Integrated circuit having a high cell density
    Patent number: 11437319
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • BACKSIDE CONDUCTING LINES IN INTEGRATED CIRCUITS
    Publication number: 20220254770
    Abstract: An integrated circuit includes a first-type active-region structure, a second-type active-region structure on a substrate, and a plurality of gate-conductors. The integrated circuit also includes a backside horizontal conducting line in a backside first conducting layer below the substrate, a backside vertical conducting line in a backside second conducting layer below the backside first conducting layer, and a pin-connector for a circuit cell. The pin-connector is directly connected between the backside horizontal conducting line and the backside vertical conducting line. The backside horizontal conducting line extends across a vertical boundary of the circuit cell.
    Type: Application
    Filed: June 10, 2021
    Publication date: August 11, 2022
    Inventors: Wei-An LAI, Shih-Wei PENG, Te-Hsin CHIU, Jiann-Tyng TZENG, Chung-Hsing WANG
  • METHOD OF GENERATING NETLIST INCLUDING PROXIMITY-EFFECT-INDUCER (PEI) PARAMETERS
    Publication number: 20220245318
    Abstract: For a method of manufacturing a semiconductor device, a corresponding layout diagram is stored on a non-transitory computer-readable medium, the layout diagram being arranged relative to first and second perpendicular directions, the layout diagram including cells such that, for a subset of the cells, each subject one of the cells (subject cell) in the subset has a neighborhood including first and second neighbor cells on corresponding first and second sides of the subject cell relative to the first direction. The method includes: for each subject cell in the subset, generating a sidefile which represents neighborhood-specific proximity-effect information.
    Type: Application
    Filed: June 22, 2021
    Publication date: August 4, 2022
    Inventors: Yen-Pin CHEN, Florentin DARTU, Wei-Chih HSIEH, Tzu-Hen LIN, Chung-Hsing WANG
  • INTEGRATED CIRCUIT DEVICE AND METHOD
    Publication number: 20220216270
    Abstract: An integrated circuit (IC) device includes a substrate and a circuit region over the substrate. The circuit region includes at least one active region extending along a first direction, at least one gate region extending across the at least one active region and along a second direction transverse to the first direction, and at least one first input/output (IO) pattern configured to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction.
    Type: Application
    Filed: January 4, 2021
    Publication date: July 7, 2022
    Inventors: Meng-Kai HSU, Jerry Chang Jui KAO, Chin-Shen LIN, Ming-Tao YU, Tzu-Ying LIN, Chung-Hsing WANG
  • CLOCK SIGNAL DISTRIBUTION SYSTEM, INTEGRATED CIRCUIT DEVICE AND METHOD
    Publication number: 20220214712
    Abstract: A clock distribution system includes a clock mesh structure which has a plurality of first metal patterns extending along a first axis, a plurality of second metal patterns extending along a second axis, a plurality of third metal patterns extending along a third axis. The plurality of first metal patterns, the plurality of second metal patterns, and the plurality of third metal patterns are electrically coupled with each other. The second axis is transverse to the first axis. The third axis is oblique to both the first axis and the second axis.
    Type: Application
    Filed: January 4, 2021
    Publication date: July 7, 2022
    Inventors: Jerry Chang Jui KAO, Huang-Yu CHEN, Sheng-Hsiung CHEN, Jack LIU, Yung-Chen CHIEN, Wei-Hsiang MA, Chung-Hsing WANG