Abstract: An integrated circuit includes a cell layer, a first metal layer, a first conductive via, and a second conductive via. The cell layer includes first and second cells, in which the first cell is separated from the second cell by a non-zero distance. The first metal layer includes a first conductive feature and a second conductive feature, the first conductive feature overlaps the first cell and does not overlap the second cell, and the second conductive feature overlaps the second cell and does not overlap the first cell, in which the first conductive feature is aligned with the second conductive feature along lengthwise directions of the first and second conductive features. The first conductive via interconnects the cell layer and the first conductive feature of the first metal layer. The second conductive via interconnects the cell layer and the second conductive feature of the first metal layer.

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit layout design. The method includes retrieving, from a cell library, first and second cells each including a first local metal track proximate to a top boundary and a second local metal track proximate to a bottom boundary. The method includes placing, by a processor, the first and second cells in a layout area including global metal tracks of first and second types. Each global metal track of the first type and each global metal tracks of the second type alternate between one another in the layout area. The first and second local metal tracks of the first cell is aligned with adjacent first global metal track of the first and second types, respectively. The first and second local metal tracks of the second cell is aligned with adjacent second global metal track of the first and second types, respectively.

Abstract: A method includes assigning a first color group to a first routing track of the layout. The method further includes assigning a second color group to a second routing track of the layout. The method includes assigning the first color group to a third routing track of the layout, wherein the second routing track is between the first routing track and the third routing track. The method further includes assigning a first color from the first color group to a first conductive element along the first routing track. The method further includes assigning a second color from the first color group to a second conductive element along the first routing track. The method further includes assigning a third color from the second color group to a third conductive element on the second routing track, wherein the third color is different from each of the first color and the second color.

Abstract: A method (of manufacturing a semiconductor device) includes, for a layout diagram stored on a non-transitory computer-readable medium, generating the layout diagram including: populating a row which extends in a first direction with a group of cells, each cell representing a circuit, and first and second side boundaries of each cell being substantially parallel and extending in a second direction which is substantially perpendicular to the first direction; locating, relative to the first direction, cells so that neighboring ones of the cells are substantially abutting; and reducing an aggregate leakage tendency of the group by performing at least one of the following, (A) changing an orientation of at least one of the cells, or (B) changing locations correspondingly of at least two of the cells.

Abstract: A method and system for manufacturing a circuit is disclosed.

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit layout design. The method includes retrieving, from a cell library, first and second cells each including a first local metal track proximate to a top boundary and a second local metal track proximate to a bottom boundary. The method includes placing, by a processor, the first and second cells in a layout area including global metal tracks of first and second types. Each global metal track of the first type and each global metal tracks of the second type alternate between one another in the layout area. The first and second local metal tracks of the first cell is aligned with adjacent first global metal track of the first and second types, respectively. The first and second local metal tracks of the second cell is aligned with adjacent second global metal track of the first and second types, respectively.

Abstract: A method for manufacturing an integrated circuit includes determining a static probability pattern of a circuit cell in a timing path of the integrated circuit; determining a timing delay of the circuit cell along the timing path according to the static probability pattern and a pattern based timing database, wherein the pattern based timing database indicates a plurality of reference delays of each timing arc of the circuit cell characterized in response to a plurality of input stress patterns respectively; and manufacturing the integrated circuit according to the timing delay of the circuit cell along the timing path.

Abstract: An integrated circuit includes a first set of devices, a set of metal layers and a header circuit. The first set of devices are configured to operate on a first supply voltage, and are located on a first layer of the integrated circuit. The set of metal layers are above the first layer, and includes a first metal layer and a second metal layer. The first metal layer extends in at least a first direction and a second direction. The header circuit is above the first set of devices. At least a portion of the header circuit is positioned between the first metal layer and the second metal layer. The header circuit is configured to provide the first supply voltage to the first set of devices, and is configured to be coupled to a second voltage supply having a second supply voltage different from the first supply voltage.

Abstract: A method (of revising an initial layout diagram of a wire routing arrangement) includes: identifying, in a first conductance layer of the initial layout diagram, a routed pattern and a dummy pattern, each of which extends in a first direction; the routed patterns being functional in a representation of a circuit; the dummy patterns being non-functional in the representation of the circuit; and revising to form a revised layout diagram, the revising including adding first and second jumper patterns, into a second conductance layer, which extend in a second direction substantially perpendicular to the first direction, and adding via patterns, into an interconnection layer between the first and second conductance layers, which represent (A) connections between the first jumper pattern and first ends of the corresponding routed and dummy patterns, and (B) connections between the second jumper pattern and second ends of the corresponding routed and dummy patterns.

Abstract: A method includes identifying the first path as a target path, wherein an operation speed of the target path is adjusted from the corner case; deriving and outputting first values from the lookup table by indexing the lookup table with a threshold voltage associated with the first path identified as the target path as the main threshold voltage and a threshold voltage associated with the second path as the slave threshold voltage; calculating a first extra time based on the first values and first cell delays associated with the first path.

Abstract: A method (of generating a layout diagram of a conductive line structure includes: determining that a first set of first to fourth short pillar patterns (which represent portions of an M(i) layer of metallization and are located relative to a grid), violates a minimum transverse-routing (TVR) distance of alpha-direction-separation, wherein (1) the grid has orthogonal alpha and beta tracks, and (2) the short pillar patterns have long axes which are substantially co-track aligned with a first one of the alpha tracks and have a first distance (of alpha-direction-separation between immediately adjacent members of the first set) which is less than the TVR distance; and merging pairings of the first & second and third & fourth short pillar patterns into corresponding first and second medium pillar patterns which have a second distance of alpha-direction-separation therebetween; the second value being greater than the TVR distance.

Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes forming a first partition by selecting at least one in-boundary PG cell from the group of PG cells, adding at least one out-boundary PG cell from the group of PG cells into the first partition, forming a second partition by selecting the remaining in-boundary PG cells and the remaining out-boundary PG cells in the group of PG cells, calculating the total area of the in-boundary PG cells in the first partition, calculating the total area of the out-boundary PG cells in the first partition, calculating the total area of the in-boundary PG cells in the second partition, calculating the total area of the out-boundary PG cells in the second partition, and calculating the difference between the total areas of in-boundary PG cells in the first partition and the out-boundary PG cells in the first partition.

Abstract: An integrated circuit includes a cell layer, a first metal layer, and a first conductive via. The cell layer includes first and second cells, each of which is configured to perform a circuit function. The first metal layer is above the cell layer and includes a first conductive feature that extends from the first cell into the second cell and that is configured to receive a supply voltage. A first conductive via interconnects the cell layer and the metal layer.

Abstract: A method performed by at least one processor includes: accessing a layout of an integrated circuit (IC), the layout comprising a resistor-capacitor (RC) netlist comprising a plurality of circuit nodes; identifying an RC network in the RC netlist; determining a characterization matrix corresponding to the RC network; updating the RC netlist by replacing the RC network with the characterization matrix; and calculating voltages and currents of the plurality of circuit nodes based on the updated RC netlist.

Abstract: A method for forming an integrated device is provided. The method includes the following operations. A first circuit layout having a first power path and a second power path is provided. The first power path and the second power path are aligned in a first direction. A first pitch between the first power path and the second power path is analyzed. It is determined whether the first pitch is less than a threshold pitch. If the first pitch is less than the threshold pitch, the second power path is modified in a second direction. The second direction is perpendicular to the first direction.

Abstract: A method includes generating a first timing library for a first set of circuit elements for a first set of input parameters. Generating the first timing library includes determining device characteristics for each of the circuit elements in the first set of circuit elements and storing the determined device characteristics in a database. A second timing library is generated for a second set of circuit elements for a second set of input parameters. The second timing library is generated by using one or more of the determined device characteristics previously stored in the database. A circuit is formed on a substrate. The circuit includes at least one of the first set of circuit elements or the second set of circuit elements.

Abstract: A method of designing a layout includes assigning a first color group to a plurality of first routing tracks. The method includes assigning a second color group to a plurality of second routing tracks. A first routing track is between adjacent second routing tracks. The method includes assigning a color from the first color group to each default conductive element along each first routing track. A color of a first default conductive element along each first routing track is different from a color of an adjacent default conductive element along a same first routing track. The method includes assigning a color from the second color group to each default conductive element along each second routing track. A color of a first default conductive element along each second routing track is different from a color of an adjacent default conductive element along a same second routing track.

Abstract: In some embodiments, a plurality of first input waveforms having a same first input transition characteristic and different first tail characteristics are obtained. A first cell is characterized using the plurality of first input waveforms to create a plurality of corresponding first entries associated with the first input transition characteristic in a library. A design layout is generated based on performing circuit simulation using at least one entry of the plurality of first entries. An integrated circuit (IC) chip is manufactured using the design layout.

Abstract: A method of forming an integrated circuit is provided. The method includes several operations. A semiconductor substrate is received, and a conductive grid is disposed over the semiconductor substrate, wherein the conductive grid includes a plurality of non-continuous conductive lines. A plurality of first conductive lines and a plurality of second conductive lines are selected from the plurality of non-continuous conductive lines. The plurality of second conductive lines is replaced by a plurality of third conductive lines respectively, wherein a space between adjacent third conductive lines is greater than a space between adjacent second conductive lines. A system configured to perform the method is also provided.