Abstract: A method of designing an integrated circuit device includes receiving an initial design of an integrated circuit, including a selection and location of a functional group of integrated circuit components, a power grid with multiple layers of conductive lines for supplying power to the components, and vias of one or more initial sizes interconnecting the conductive lines of different layers. The method further includes determining, based on a predetermined criterion such as the existence of unoccupied space for a functional unit, that a via modification can be made. The method further includes substituting the one or more of the via with a modified via of a larger cross-sectional area or a plurality of vias having a larger total cross-sectional area than the initial via. The method further includes confirming that the modified design complies with a predetermined set of design rules.

Abstract: A method includes determining a cell loading of a cell in an integrated circuit (IC) layout diagram. Based on the determined cell loading, a power parameter associated with the cell is determined. In response to the determined power parameter exceeding a design criterion, at least one of altering a placement of the cell in the IC layout diagram or modifying a power delivery path to the cell is performed. At least one of the determining the cell loading, the determining the power parameter, the altering the placement of the cell, or the modifying the power delivery path is executed by a processor.

Abstract: An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A total length of the second metal lines of the second net is shorter than a total length of the first metal lines of the first net. A count of the f first metal vias of the first net is less than a count of the second metal vias of the second net.

Abstract: A method (of revising an initial layout diagram of a wire routing arrangement, the initial layout diagram and versions thereof being stored on a non-transitory computer-readable medium) includes identifying, in a first conductance layer of the initial layout diagram, a routed pattern and a dummy pattern, each of which extends in a first direction and revising to form a revised layout diagram. The routed patterns are functional in a representation of a circuit and the dummy patterns are non-functional in the representation of the circuit. The revising includes connecting first ends of the corresponding routed and dummy patterns and connecting second ends of the corresponding routed and dummy patterns.

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes partitioning a layout area into one or more contiguous units, where each unit includes a plurality of placement sites. The method also includes mapping a first set of pin locations and a second set of pin locations to each of the one or more contiguous units. The method further includes placing a cell in the one or more contiguous units, where the cell is retrieved from a cell library that includes a plurality of pin locations for the cell. The placement of the cell is based on an allocation of one or more pins associated with the cell to at least one of a pin track from the first plurality of pin locations, a pin track from second plurality of pin locations, or a combination thereof.

Abstract: A method of generating an IC layout diagram includes abutting a first row of cells with a second row of cells along a border, the first row including first and second active sheets, the second row including third and fourth active sheets, the active sheets extending along a row direction and having width values. The active sheets are overlapped with first through fourth back-side via regions, the first active sheet width value is greater than the third active sheet width value, a first back-side via region width values is greater than a third back-side via region width value, and a value of a distance from the first active sheet to the border is less than a minimum spacing rule for metal-like defined regions. At least one of abutting the first row with the second row or overlapping the active sheets with the back-side via regions is performed by a processor.

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit layout design. The method includes retrieving, from a cell library, first and second cells each including a first local metal track proximate to a top boundary and a second local metal track proximate to a bottom boundary. The method includes placing, by a processor, the first and second cells in a layout area including global metal tracks of first and second types. Each global metal track of the first type and each global metal tracks of the second type alternate between one another in the layout area. The first and second local metal tracks of the first cell is aligned with adjacent first global metal track of the first and second types, respectively. The first and second local metal tracks of the second cell is aligned with adjacent second global metal track of the first and second types, respectively.

Abstract: A method for timing optimization is disclosed. The method includes obtaining information on timing of paths in a chip, the information including a mean of slacks and a sigma of slacks of each of the paths; determining a sigma margin (SM) value each of the paths, the SM value being obtained by dividing the mean by the sigma; dividing the paths into groups based on SM values, an SM value of a path in one of the groups being different from that of a path in another one of the groups; and determining a yield requirement that indicates the maximum number of paths allowable in each group in order to achieve a predetermined yield.

Abstract: Power grid of an integrated circuit (IC) is provided. A plurality of first power lines are formed in a first metal layer. A plurality of second power lines are formed in the first metal layer and parallel to the first power lines, and the first and second power lines are interlaced in the first metal layer. A plurality of third power lines formed in a second metal layer, and the third power lines are perpendicular to the first power lines. A plurality of fourth power lines are formed in the second metal layer and parallel to the third power lines, and the third and fourth power lines are interlaced in the second metal layer. Distances from each of the third power lines to two adjacent fourth power lines are different, and distances from each of the fourth power lines to two adjacent third power lines are the same.

Abstract: Systems and methods for context aware circuit design are described herein. A method includes: identifying at least one cell to be designed into a circuit; identifying at least one context parameter having an impact to layout dependent effect of the circuit; generating, for each cell and for each context parameter, a plurality of abutment environments associated with the cell; estimating, for each cell and each context parameter, a sensitivity of at least one electrical property of the cell to the context parameter by generating a plurality of electrical property values of the cell under the plurality of abutment environments; and determining whether each context parameter is a key context parameter for a static analysis of the circuit, based on the sensitivity of the at least one electrical property of each cell and based on at least one predetermined threshold.

Abstract: A method of a layout diagram (of a conductive line structure for an IC) including: for a first set of pillar patterns included in an initial layout diagram that represents portions of an M(i) layer of metallization and where i is a non-negative number, the first set including first and second pillar patterns which are non-overlapping of each other, which have long axes that are substantially collinear with a reference line, and which have a first distance of separation, determining a first distance of separation as between corresponding immediately adjacent members of the first set; recognizing that the first distance is less than a transverse routing (TVR) separation threshold for an M(i+j) layer of metallization, where j is an integer and j?2; and increasing the first distance so as to become a second distance which is greater than the TVR separation threshold of the M(i+j) layer.

Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.

Abstract: An IC structure includes first, second, third and fourth transistors on a substrate, and first and second metallization layers over the transistors. The first metallization layer has a plurality of first metal lines extending laterally along a first direction and having a first line width measured in a second direction. One or more of the first metal lines are part of a first net electrically connecting the first and second transistors. The second metallization layer has a plurality of second metal lines extending laterally along the second direction and having a second line width measured in the first direction and less than the first line width. One or more of the second metal lines are part of a second net electrically connecting the third and fourth transistors, and a total length of the second net is less than a total length of the first net.

Abstract: An integrated circuit includes a first set of devices, a set of metal layers and a header circuit. The first set of devices are configured to operate on a first supply voltage, and are located on a first layer of the integrated circuit. The set of metal layers are above the first layer, and includes a first metal layer and a second metal layer. The first metal layer extends in at least a first direction and a second direction. The header circuit is above the first set of devices. At least a portion of the header circuit is positioned between the first metal layer and the second metal layer. The header circuit is configured to provide the first supply voltage to the first set of devices, and is configured to be coupled to a first voltage supply having the first supply voltage.

Abstract: A system includes a library, a processor and an output interface. The library contains at least one leakage lookup table related to leakage current values for different cell abutment cases of abutted cells in a semiconductor device. The cell abutment cases are associated with terminal types of cell edges of the abutted cells. The processor is configured to perform an analysis to detect boundaries between the abutted cells, identify attributes associated with the terminal types of the cell edges, identify the cell abutment cases based on the attributes, and calculate maximal boundary leakages between the abutted cells based on leakage current values associated with the cell abutment cases and leakage probabilities associated with the cell abutment cases. The output interface is for outputting boundary leakages corresponding to the maximal boundary leakages in the semiconductor device. A method is also disclosed herein.

Abstract: A method includes: identifying attributes that are associated with cell edges of abutted cells in a layout of a semiconductor device, wherein the attributes include at least one of terminal types of the cell edges; determining at least one minimal boundary leakage of the abutted cells based on the attributes, for adjustment of the layout of the semiconductor device. A system is also disclosed herein.

Abstract: In a method, cell placement is performed to place a plurality of cells into a region of an integrated circuit (IC). A thermal analysis is performed to determine whether the region of the IC is thermally stable at an operating condition. In response to a determination that the region of the IC is thermally unstable, at least one of a structure or the operating condition of the region of the IC is changed. After the thermal analysis, routing is performed to route a plurality of nets interconnecting the placed cells. At least one of the cell placement, the thermal analysis, the changing or the routing is executed by a processor.

Abstract: A method (of revising an initial layout diagram of a wire routing arrangement) includes: identifying, in a first conductance layer of the initial layout diagram, a routed pattern and a dummy pattern, each of which extends in a first direction; the routed patterns being functional in a representation of a circuit; the dummy patterns being non-functional in the representation of the circuit; and revising to form a revised layout diagram, the revising including adding first and second jumper patterns, into a second conductance layer, which extend in a second direction substantially perpendicular to the first direction, and adding via patterns, into an interconnection layer between the first and second conductance layers, which represent (A) connections between the first jumper pattern and first ends of the corresponding routed and dummy patterns, and (B) connections between the second jumper pattern and second ends of the corresponding routed and dummy patterns.

Abstract: A mechanism for adjusting the tension of a flexible transmission component, comprising: a driver; a follower, with a center distance between the center of the driver and the center of the follower; a flexible transmission component, which is a closed loop passing around the driver and the follower; a first base connecting with the driver, wherein aid first base can move in a direction of movement parallel to the center distance and away from and/or forward to the follower; a second base connecting with the follower; and at least one elastic component connecting the first base and the second base.

Abstract: A method and system for manufacturing a circuit is disclosed.