Abstract: A method includes assigning a first color group to a first routing track of the layout. The method further includes assigning a second color group to a second routing track of the layout. The method includes assigning the first color group to a third routing track of the layout, wherein the second routing track is between the first routing track and the third routing track. The method further includes assigning a first color from the first color group to a first conductive element along the first routing track. The method further includes assigning a second color from the first color group to a second conductive element along the first routing track. The method further includes assigning a third color from the second color group to a third conductive element on the second routing track, wherein the third color is different from each of the first color and the second color.

Abstract: A semiconductor structure includes a power grid layer (including a first metallization layer) and a set of cells. The first metallization layer includes: conductive first and second portions which provide correspondingly a power-supply voltage and a reference voltage, and which have corresponding long axes oriented substantially parallel to a first direction; and conductive third and fourth portions which provide correspondingly the power-supply voltage and the reference voltage, and which have corresponding long axes oriented substantially parallel to a second direction substantially perpendicular to the first direction. The set of cells is located below the PG layer. Each cell is monostate cell which lacks an input signal and has a single output state. The cells are arranged to overlap at least one of the first and second portions in a repeating relationship with respect to at least one of the first or second portions of the first metallization layer.

Abstract: A method for forming an integrated device includes following operations. It is provided a first circuit having a first connecting path in a metal line layer, a second connecting path, and a third connecting path. The second connecting path is electrically connected to a first connecting portion of the first connecting path in the metal line layer. The third connecting path is electrically coupled to a second connecting portion of the first connecting path in the metal line layer. An electromigration (EM) data of the first connecting path is analyzed to determine if a third connecting portion in the metal line layer between the first connecting portion and the second connecting portion induces EM phenomenon. The first circuit is modified to generate a second circuit when the third connecting portion induces EM phenomenon. The integrated device is generated according to the second circuit.

Abstract: A method and system for manufacturing a circuit is disclosed.

Abstract: An integrated circuit includes a cell layer, a first metal layer, a first conductive via, and a second conductive via. The cell layer includes first and second cells, in which the first cell is separated from the second cell by a non-zero distance. The first metal layer includes a first conductive feature and a second conductive feature, the first conductive feature overlaps the first cell and does not overlap the second cell, and the second conductive feature overlaps the second cell and does not overlap the first cell, in which the first conductive feature is aligned with the second conductive feature along lengthwise directions of the first and second conductive features. The first conductive via interconnects the cell layer and the first conductive feature of the first metal layer. The second conductive via interconnects the cell layer and the second conductive feature of the first metal layer.

Abstract: A method includes: accessing a design data of an integrated circuit (IC), wherein the design data includes a transistor layer and a plurality of metal layers over the transistor layer; assigning a bin size for each of the metal layers based on layout properties of the respective metal layers, wherein the bin sizes are progressively larger from a bottom layer to a top layer of the metal layers; performing resource planning on the transistor layer and each of the metal layers according to the assigned bin sizes of the respective metal layers; and updating the design data according to the resource planning. At least one of the accessing, assigning, performing and updating steps is conducted by at least one processor.

Abstract: A FIT evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC comprising a number of metal lines and a number of VIAs; picking a number of nodes along the metal lines; dividing each of the metal lines into a number of metal segments based on the nodes; and determining a FIT value for each of the metal segments or VIAs to verify the layout and fabricate the IC.

Abstract: A semiconductor device includes: a power grid (PG) arrangement including: a conductive layer M(i) including segments which are conductive, where i is an integer and i?0; and a conductive layer M(i+1) over the conductive layer M(i), the conductive layer M(i+1) including segments which are conductive; the M(i) segments including first and second segments designated correspondingly for first and second reference voltages, the first and second segments being interspersed and substantially parallel to a first direction; and the segments in the conductive layer M(i+1) including third and fourth segments designated correspondingly for the first and second reference voltages; the third and fourth segments being interspersed and substantially parallel to a perpendicular second direction; and wherein the segments in the conductive layer M(i+1) are arranged substantially asymmetrically such that each fourth segment is located, relative to the first direction, substantially asymmetrically between corresponding adjacent o

Abstract: A method (of manufacturing a semiconductor device) includes, for a layout diagram stored on a non-transitory computer-readable medium, generating the layout diagram including: populating a row which extends in a first direction with a group of cells, each cell representing a circuit, and first and second side boundaries of each cell being substantially parallel and extending in a second direction which is substantially perpendicular to the first direction; locating, relative to the first direction, cells so that neighboring ones of the cells are substantially abutting; and reducing an aggregate leakage tendency of the group by performing at least one of the following, (A) changing an orientation of at least one of the cells, or (B) changing locations correspondingly of at least two of the cells.

Abstract: A method of forming a semiconductor device includes: providing a first circuit having a plurality of circuit cells; analyzing a loading capacitance on a first pin cell connecting a first circuit cell and a second circuit cell in the plurality of circuit cells to determine if the loading capacitance of the first pin cell is larger than a first predetermined capacitance; replacing the first pin cell by a second pin cell for generating a second circuit when the loading capacitance is larger than the first predetermined capacitance, wherein the second pin cell is different from the first pin cell; and generating the semiconductor device according to the second circuit.

Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

Abstract: A semiconductor structure includes a power grid layer (including a first metallization layer) and a set of cells. The first metallization layer includes: conductive first and second portions which provide correspondingly a power-supply voltage and a reference voltage, and which have corresponding long axes oriented substantially parallel to a first direction; and conductive third and fourth portions which provide correspondingly the power-supply voltage and the reference voltage, and which have corresponding long axes oriented substantially parallel to a second direction substantially perpendicular to the first direction. The set of cells is located below the PG layer. Each cell lacks a conductive structure which is included in the first metallization layer. The cells are arranged to overlap at least one of the first and second portions in a repeating relationship with respect to at least one of the first or second portions of the first metallization layer.

Abstract: A method for mitigating extreme ultraviolet (EUV) mask defects is disclosed. The method includes the steps of providing a wafer blank, identifying a first plurality of defects on the wafer blank, providing an EUV mask design on top of the wafer blank, identifying non-critical blocks with corresponding stretchable zones on the EUV mask design, overlapping the EUV blank with the EUV mask design, identifying a second plurality of defects, the second plurality of defects are solved, identifying a third plurality of defects, the third plurality of defects are not solved, adjusting the relative locations of the EUV mask design and the EUV blank to solve at least one of the third plurality of defects, and adjusting the locations of at least one of the non-critical blocks within corresponding stretchable zones to solve at least one of the third plurality of defects.

Abstract: An integrated circuit that includes a first row having a first height, with a first cell in the first row that has the first height. The integrated circuit further includes a second row having a second height, where the first height is not an integer multiple of the second height. A second cell is in the second row that has the second height.

Abstract: A method of designing an integrated circuit device includes receiving an initial design of an integrated circuit, including a selection and location of a functional group of integrated circuit components, a power grid with multiple layers of conductive lines for supplying power to the components, and vias of one or more initial sizes interconnecting the conductive lines of different layers. The method further includes determining, based on a predetermined criterion such as the existence of unoccupied space for a functional unit, that a via modification can be made. The method further includes substituting the one or more of the via with a modified via of a larger cross-sectional area or a plurality of vias having a larger total cross-sectional area than the initial via. The method further includes confirming that the modified design complies with a predetermined set of design rules.

Abstract: A method of forming an integrated circuit is provided. The method includes several operations. A semiconductor substrate is received, and a conductive grid is disposed over the semiconductor substrate, wherein the conductive grid includes a plurality of non-continuous conductive lines. A plurality of first conductive lines and a plurality of second conductive lines are selected from the plurality of non-continuous conductive lines. The plurality of second conductive lines is replaced by a plurality of third conductive lines respectively, wherein a space between adjacent third conductive lines is greater than a space between adjacent second conductive lines. A system configured to perform the method is also provided.

Abstract: A method includes: identifying a timing path of a logic circuit; determining a Boolean expression at an internal node in the timing path; providing a DC vector having a plurality of forms; determining a Boolean value at the internal node for each of the forms based on the Boolean expression; determining a quantity of stressed transistors in the timing path for each of the forms separately based on the respective Boolean value; and determining a best-case form, associated with an aging effect of the logic circuit, and a worst-case form, associated with the aging effect, out of the forms based on the quantities of stressed transistors.

Abstract: An integrated circuit structure includes: an integrated circuit structure includes: a first plurality of cell rows extending in a first direction, and a second plurality of cell rows extending in the first direction. Each of the first plurality of cell rows has a first row height and comprises a plurality of first cells disposed therein. Each of the second plurality of cell rows has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction. The plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction. At least one active region of the first and second pluralities of active regions has a width varying along the first direction.

Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

Abstract: A method includes identifying a timing path in a transistor level from a graph diagram; calculating a plurality of aging costs associated with the timing path based on a plurality of forms of a DC vector; identifying a first form, associated with a first aging cost of the aging costs, from the forms; and identifying a second form, associated with a second aging cost less than the first aging cost, from the forms.