Abstract: Substrate-less lateral diode integrated circuit structures, and methods of fabricating substrate-less lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin or a stack of nanowires. A plurality of P-type epitaxial structures is over the fin or stack of nanowires. A plurality of N-type epitaxial structures is over the fin or stack of nanowires. One or more spacings are in locations over the fin or stack of nanowires, a corresponding one of the one or more spacings extending between neighboring ones of the plurality of P-type epitaxial structures and the plurality of N-type epitaxial structures.

Abstract: Substrate-less nanowire-based lateral diode integrated circuit structures, and methods of fabricating substrate-less nanowire-based lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a stack of nanowires. A plurality of P-type epitaxial structures is over the stack of nanowires. A plurality of N-type epitaxial structures is over the stack of nanowires. One or more gate structures is over the stack of nanowires. A semiconductor material is between and in contact with vertically adjacent ones of the stack of nanowires.

Abstract: Substrate-less silicon controlled rectifier (SCR) integrated circuit structures, and methods of fabricating substrate-less silicon controlled rectifier (SCR) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin portion and a second fin portion that meet at a junction. A plurality of gate structures is over the first fin portion and a second fin portion. A plurality of P-type epitaxial structures and N-type epitaxial structures is between corresponding adjacent ones of the plurality of gate structures. Pairs of the P-type epitaxial structures alternate with pairs of the N-type epitaxial structures.

Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

Abstract: Integrated circuitry comprising high voltage (HV) and low voltage (LV) ribbon or wire (RoW) transistor stack structures. In some examples, a gate electrode of the HV and LV transistor stack structures may include the same work function metal. A metal oxide may be deposited around one or more channels of the HV transistor stack, thereby altering the dipole properties of the gate insulator stack from those of the LV transistor stack structure.

Abstract: Substrate-less electrostatic discharge (ESD) integrated circuit structures, and methods of fabricating substrate-less electrostatic discharge (ESD) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin and a second fin protruding from a semiconductor pedestal. An N-type region is in the first and second fins. A P-type region is in the semiconductor pedestal. A P/N junction is between the N-type region and the P-type region, the P/N junction on or in the semiconductor pedestal.

Abstract: Substrate-free integrated circuit structures, and methods of fabricating substrate-free integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin, a plurality of gate structures over the fin, and a plurality of alternating P-type epitaxial structures and N-type epitaxial structures between adjacent ones of the plurality of gate structures.

Abstract: A transistor structure includes a first channel layer over a second channel layer, where the first and the second channel layers include monocrystalline silicon. An epitaxial source material is coupled to a first end of the first and second channel layers. An epitaxial drain material is coupled to a second end of the first and second channel layers, a gate electrode is between the epitaxial source material and the epitaxial drain material, and around the first channel layer and around the second channel layer. The transistor structure further includes a first gate dielectric layer between the gate electrode and each of the first channel layer and the second channel layer, where the first gate dielectric layer has a first dielectric constant. A second gate dielectric layer is between the first gate dielectric layer and the gate electrode, where the second gate dielectric layer has a second dielectric constant.

Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Abstract: Gate-all-around integrated circuit structures having an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator substrate, are described. For example, an integrated circuit structure includes a semiconductor fin on an insulator substrate. A vertical arrangement of horizontal nanowires is over the semiconductor fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal nanowires, and the gate stack is overlying a channel region of the semiconductor fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal nanowires and the semiconductor fin.

Abstract: Gate-all-around integrated circuit structures having low aspect ratio isolation structures and subfins, and method of fabricating gate-all-around integrated circuit structures having low aspect ratio isolation structures and subfins, are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first subfin. A second vertical arrangement of horizontal nanowires is above a second subfin laterally adjacent the first subfin. An isolation structure is laterally between the first subfin and the second subfin, the isolation structure having a maximum height and a maximum width with a maximum height to maximum width ratio of less than 3:1.

Abstract: Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.

Abstract: Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.

Abstract: Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.

Abstract: Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the semiconductor island. A gate stack is over the vertical arrangement of horizontal nanowires.

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Abstract: A method of forming metal lines that are aligned to underlying metal features that includes forming a neutral layer atop a hardmask layer that is overlying a dielectric layer. The neutral layer is composed of a neutral charged di-block polymer. Patterning the neutral layer, the hardmask layer and the dielectric layer to provide openings that are filled with a metal material to provide metal features. A self-assembled di-block copolymer material is deposited on a patterned surface of the neutral layer and the metal features. The self-assembled di-block copolymer material includes a first block composition with a first affinity for alignment to the metal features. The first block composition of the self-assembled di-block copolymer is converted to a metal that is self-aligned to the metal features.