Patents by Inventor Chung Hsun Lin

Chung Hsun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FINFET PCM ACCESS TRANSISTOR HAVING GATE-WRAPPED SOURCE AND DRAIN REGIONS
    Publication number: 20170053966
    Abstract: Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET) device. The method includes forming at least one source region having multiple sides, forming at least one drain region having multiple sides, forming at least one channel region having multiple sides, forming at least one gate region around the multiple sides of the at least one channel region and forming the at least one gate region around the multiple sides of the at least one drain region.
    Type: Application
    Filed: August 21, 2015
    Publication date: February 23, 2017
    Inventors: Chung H. Lam, Chung-Hsun Lin, Darsen D. Lu, Philip J. Oldiges
  • Asymmetric high-K dielectric for reducing gate induced drain leakage
    Patent number: 9577061
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: February 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw
  • Asymmetric high-K dielectric for reducing gate induced drain leakage
    Patent number: 9570354
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw
  • Asymmetric high-k dielectric for reducing gate induced drain leakage
    Patent number: 9559010
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: January 31, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw
  • Asymmetric finFET memory access transistor
    Patent number: 9553173
    Abstract: A field effect transistor device comprises a semiconductor substrate, a doped source layer arranged on the semiconductor substrate, an insulator layer arranged on the doped source layer, a fin arranged on the insulator layer, a source region extension portion extending from the doped source layer and through the fin, a gate stack arranged over a channel region of the fin and adjacent to the source region extension portion, a drain region arranged on the fin adjacent to the gate stack; the drain region having a graduated doping concentration.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: January 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chung H. Lam, Chung-hsun Lin, Darsen D. Lu, Philip J. Oldiges
  • INCREASED CONTACT AREA FOR FINFETS
    Publication number: 20170012129
    Abstract: A method for forming fin field effect transistors includes epitaxially growing source and drain (S/D) regions on fins, the S/D regions including a diamond-shaped cross section and forming a dielectric liner over the S/D regions. A dielectric fill is etched over the S/D regions to expose a top portion of the diamond-shaped cross section. The fins are recessed into the diamond-shaped cross section. A top portion of the diamond-shaped cross section of the S/D regions is exposed. A contact liner is formed on the top portion of the diamond-shaped cross section of the S/D regions and in a recess where the fins were recessed. Contacts are formed over surfaces of the top portion and in the recess.
    Type: Application
    Filed: July 9, 2015
    Publication date: January 12, 2017
    Inventors: Veeraraghavan S. Basker, Chung-Hsun Lin, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Asymmetric high-k dielectric for reducing gate induced drain leakage
    Patent number: 9543213
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: January 10, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw
  • Strained semiconductor nanowire
    Patent number: 9530876
    Abstract: At least one semiconductor nanowire laterally abutted by a pair of semiconductor pad portions is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor nanowire such that the at least one semiconductor nanowire is suspended. A temporary fill material is deposited over the at least one semiconductor nanowire, and is planarized to physically expose top surfaces of the pair of semiconductor pad portions. Trenches are formed within the pair of semiconductor pad portions, and are filled with stress-generating materials. The temporary fill material is subsequently removed. The at least one semiconductor nanowire is strained along the lengthwise direction with a tensile strain or a compressive strain.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: December 27, 2016
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • III-V MOSFETs with halo-doped bottom barrier layer
    Patent number: 9530860
    Abstract: Techniques for controlling short channel effects in III-V MOSFETs through the use of a halo-doped bottom (III-V) barrier layer are provided. In one aspect, a method of forming a MOSFET device is provided. The method includes the steps of: forming a III-V barrier layer on a substrate; forming a III-V channel layer on a side of the III-V barrier layer opposite the substrate, wherein the III-V barrier layer is configured to confine charge carriers in the MOSFET device to the III-V channel layer; forming a gate stack on a side of the III-V channel layer opposite the III-V barrier layer; and forming halo implants in the III-V barrier layer on opposite sides of the gate stack. A MOSFET device is also provided.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: December 27, 2016
    Assignee: Globalfoundries, Inc.
    Inventors: Pranita Kerber, Chung-Hsun Lin, Amlan Majumdar, Jeffrey W. Sleight
  • CHEMOEPITAXY ETCH TRIM USING A SELF ALIGNED HARD MASK FOR METAL LINE TO VIA
    Publication number: 20160365280
    Abstract: A method of forming metal lines that are aligned to underlying metal features that includes forming a neutral layer atop a hardmask layer that is overlying a dielectric layer. The neutral layer is composed of a neutral charged di-block polymer. Patterning the neutral layer, the hardmask layer and the dielectric layer to provide openings that are filled with a metal material to provide metal features. A self-assembled di-block copolymer material is deposited on a patterned surface of the neutral layer and the metal features. The self-assembled di-block copolymer material includes a first block composition with a first affinity for alignment to the metal features. The first block composition of the self-assembled di-block copolymer is converted to a metal that is self-aligned to the metal features.
    Type: Application
    Filed: June 12, 2015
    Publication date: December 15, 2016
    Inventors: Markus Brink, Michael A. Guillorn, Chung-Hsun Lin, HsinYu Tsai
  • ELECTRONIC DEVICE INCLUDING MOAT POWER METALLIZATION IN TRENCH
    Publication number: 20160358852
    Abstract: An electronic device is provided. The electronic device includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, circuitry disposed on the dielectric layer that includes interconnected cells, first contact line metallization and second contact line metallization, first power metallization disposed in-plane with or above the circuitry and second power metallization disposed in a trench defined in at least the dielectric layer. The electronic device further includes insulation disposed to insulate the second power metallization from the circuitry and the first power metallization at first locations and to permit electrical communication between the second power metallization, the circuitry and the first power metallization at second locations.
    Type: Application
    Filed: June 8, 2015
    Publication date: December 8, 2016
    Inventors: Josephine B. Chang, Leland Chang, Michael A. Guillorn, Chung-Hsun Lin, Adam M. Pyzyna
  • ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE
    Publication number: 20160268390
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Application
    Filed: May 19, 2016
    Publication date: September 15, 2016
    Inventors: Anthony I. CHOU, Arvind KUMAR, Chung-Hsun LIN, Shreesh NARASIMHA, Claude ORTOLLAND, Jonathan T. SHAW
  • ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE
    Publication number: 20160260618
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Application
    Filed: May 19, 2016
    Publication date: September 8, 2016
    Inventors: Anthony I. CHOU, Arvind KUMAR, Chung-Hsun LIN, Shreesh NARASIMHA, Claude ORTOLLAND, Jonathan T. SHAW
  • ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE
    Publication number: 20160260638
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Application
    Filed: May 19, 2016
    Publication date: September 8, 2016
    Inventors: Anthony I. CHOU, Arvind KUMAR, Chung-Hsun LIN, Shreesh NARASIMHA, Claude ORTOLLAND, Jonathan T. SHAW
  • Asymmetric high-k dielectric for reducing gate induced drain leakage
    Patent number: 9412667
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: August 9, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw
  • ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE
    Publication number: 20160203987
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Application
    Filed: March 21, 2016
    Publication date: July 14, 2016
    Inventors: Anthony I. CHOU, Arvind KUMAR, Chung-Hsun LIN, Shreesh NARASIMHA, Claude ORTOLLAND, Jonathan T. SHAW
  • ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE
    Publication number: 20160204214
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Application
    Filed: March 21, 2016
    Publication date: July 14, 2016
    Inventors: Anthony I. CHOU, Arvind KUMAR, Chung-Hsun LIN, Shreesh NARASIMHA, Claude ORTOLLAND, Jonathan T. SHAW
  • ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE
    Publication number: 20160203986
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Application
    Filed: March 21, 2016
    Publication date: July 14, 2016
    Inventors: Anthony I. CHOU, Arvind KUMAR, Chung-Hsun LIN, Shreesh NARASIMHA, Claude ORTOLLAND, Jonathan T. SHAW
  • ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE
    Publication number: 20160204209
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Application
    Filed: March 21, 2016
    Publication date: July 14, 2016
    Inventors: Anthony I. CHOU, Arvind KUMAR, Chung-Hsun LIN, Shreesh NARASIMHA, Claude ORTOLLAND, Jonathan T. SHAW
  • ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE
    Publication number: 20160203985
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Application
    Filed: March 21, 2016
    Publication date: July 14, 2016
    Inventors: Anthony I. CHOU, Arvind KUMAR, Chung-Hsun LIN, Shreesh NARASIMHA, Claude ORTOLLAND, Jonathan T. SHAW